標題: 高階助聽器晶片及系統---總計畫(I)
Advanced Hearing Aid SoC and System(I)
作者: 吳介琮
WU JIEH-TSORNG
國立交通大學電子工程學系及電子研究所
關鍵字: 助聽器;數位訊號處理器;低功率晶片系統;混合訊號式積體電路;微機電;Hearing Aids;Digital Signal Processor;Low-Power System on a Chip;Mixed-Signal Integrated Circuits;MEMS.
公開日期: 2010
摘要: 本計畫將設計並實現一個能放置於耳道內(CIC/ITC, Completely-in-Canal/In-the-Canal)的高階數位式助聽器系統。除了助聽器的一般功能,如聽力補償、噪音抑制、回饋音消除等,本計畫將開發雙耳處理技術來進一步提升助聽器的效能。 在系統部分,本計畫將繼續改良針對華語而設計的聽力補償策略,並發展聽覺認知訊號處理技術以提升語音辨識力。同時我們將開發雙耳之間的通訊技術。左右耳助聽器可藉以互相溝通,交換訊號參數以平衡並且同步雙耳的助聽器,提供助聽器方向辨識的能力。更可進一步利用雙耳訊號聯合處理開發音源分離技術以提升噪音抑制的功能。本計畫將規劃臨床測試來評估所開發的助聽器的效益。 在硬體部分,本計畫將開發助聽器專用的SoC晶片,此晶片上有「助聽器計算引擎」,配合訊號處理加速器,可執行所有的助聽器訊號處理以及各種附加功能。我們將降低工作電壓來減少功率消耗。晶片上也會包含類比電路,用來將麥克風接收的訊號轉成數位訊號,以及將數位訊號轉成類比訊號並驅動喇叭。而晶片上的電源管理電路則是將電池電源轉換成穩定的電壓電源供其他電路使用。此SoC晶片將以90 nm CMOS製程技術製作,其整體功率消耗將小於1 mW。本計畫也將開發高效能的微機電式喇叭、電感、及異質整合的微小型助聽器載具。所開發的載具可以整合聲學元件、晶片,及其他零件而成為完整之助聽器系統。
This project is to design and realize a completely-in-canal/in-the-canal (CIC/ITC) advanced digital hearing aid system. In additional to typical hearing aid functionalities, such as hearing-loss compensation, noise reduction, and echo cancellation, we will also develop binaural processing techniques to further improve the hearing aid performances. On the system design, we will continue improving the hearing-loss compensation strategy specifically designed for Chinese-speaking population. We will develop signal processing techniques rooted in understanding human hearing perception to achieve speech enhancement for hearing aid users. Furthermore, we will develop the communication technology for binaural hearing aids. Hearing aids on both the right ear and the left ear will be able to communicate and exchange signal parameters for the purpose of synchronizing and balancing them, thus preserving the directionality of the sound field. The joint processing of binaural signals can enable the acoustic source separation techniques which can be used to improve the efficiency of noise reduction. Actual clinical tryouts will be employed to evaluate the performance of the hearing aid functionalities we develop. On the hardware design, we will design several generations of hearing aid SoCs. The chips will include a digital computing engine and some hardware accelerators for executing all hearing-aid signal processing and other auxiliary functions. The digital circuits are operated under reduced supply voltage to decrease power dissipation. Also on the chip are analog circuits, including analog-to-digital converters for converting microphone signals into digital signals, digital-to-analog converters for converting digital signals to speaker sounds. The power management circuits convert battery energy into stable supplies to power other circuits on the SoC. The chips will be fabricated using a 90 nm CMOS technology. Total power consumption of each SoC chip will be less than 1 mW. We will also develop high-efficient MEMS speakers, inductors, and heterogeneous micro carrier. This micro carrier can package acoustic devices, SoC chip, and other components to form a complete hearing aid system.
官方說明文件#: NSC99-2220-E009-066
URI: http://hdl.handle.net/11536/99902
https://www.grb.gov.tw/search/planDetail?id=2118112&docId=338853
Appears in Collections:Research Plans