標題: 平行運算電子設計自動化技術研究-子計畫一：在多核心運算平台中建構應用於三維積體電路之平行設計自動化環境( I )Parallel Design Automation Environment for 3d Ics Using Multi-Core Computing Platform 作者: 黃俊達Huang Juinn-Dar國立交通大學電子工程學系及電子研究所 關鍵字: 三維可程式邏輯閘陣列;熱電阻模型;熱模擬;溫度估計;熱感知擺放演算法。;3D FPGAs;thermal resistive model;thermal modeling;temperature estimation;thermal-aware placement method. 公開日期: 2011 摘要: 在三維晶片設計流程中，溫度議題是相當重要且無法忽視的挑戰之一，也因此如何使設計流程具有熱感知能力一直都是一項重要的議題。毫無疑問的，當可程式邏輯閘陣列邁向三維架構時，溫度議題亦同時浮現。而如何精準且快速的估計溫度將會是解決此議題的重要基礎。我們根據基板、導線以及接面的材料特性來提出一系列適用於三維可程式邏輯閘陣列(3D FPGAs)的精準細微(fine-grained)熱電阻模型。而我們也提出一系列較為精簡的熱模型來加速溫度的估算速度並確保估算之精準度。此研究亦針對三維可程式化閘陣列(FPGA)架構提出兩種不須太過精確熱模型之熱感知擺放演算法－標準差法(Standard Deviation，SD)和踩地雷法(Minesweeper，MS)，兩者皆以分散區塊分布來降低熱點(hotspot)的產生。由實驗結果可以證實，我們所提出之精簡的熱模型所估算之溫度與精準細微的熱模型之計算結果相較是非常接近的；而在可接受的線長與延遲增加範圍內，SD與MS兩個方法分別降低12.1%/7.6%的最高溫度和82%/56%的溫度標準差。Temperature-aware design concept is getting crucial since the thermal issue is one of most critical challenges while implementing three-dimensional (3D) integrated circuits. Undoubtedly, the thermal issue would also be significant once FPGAs step into the 3D arena. Obviously, a method for fast and accurate temperature estimation is fundamental for solving this issue. For this purpose, we propose several thermal models dedicated to 3D FPGAs in this project. A set of precise fine-grained thermal resistive models are first constructed according to material properties of substrate, interconnect, and bonding interface. To speed up temperature evaluation, a series of simplified thermal models are then developed while still keeping estimation accuracy virtually unaltered.We also propose two fast thermal-aware placement methods for 3D FPGAs, Standard Deviation (SD) and MineSweeper (MS), without the need of detailed thermal analysis. Both are devoted to distribute power sources more evenly within a 3D FPGA to mitigate hotspots. Experiment results show that temperature calculated by the simplified models is very close to that given by the fine-grained ones； the SD and MS achieve 12.1%/7.6% reduction in maximum temperature and 82%/56% improvement in temperature deviation compared to a typical thermal-unaware placement method only at the cost of minor increase in wirelength and delay. 官方說明文件#: NSC100-2220-E009-044 URI: http://hdl.handle.net/11536/99540https://www.grb.gov.tw/search/planDetail?id=2310973&docId=361207 Appears in Collections: Research Plans