標題: 先進奈米級非對稱金氧半電晶體技術開發
Development of Advanced Nano-Scale Mosfets with Asymmetrical Source/Drain
作者: 黃調元
HUANG TIAO-YUAN
國立交通大學電子工程學系及電子研究所
關鍵字: 非對稱蕭特基薄膜電晶體;雙重微影技術;鎳矽化合物;Asymmetric Schottky-barrier (ASSB);double patterning technique;NiSi
公開日期: 2011
摘要: 本計劃將應用我們先前發展的I-line雙重微影技術,來製作與研究多種前瞻的奈米級元件。本計劃主要分為四大主題:第一、非對稱源/汲極金氧半場效電晶體,藉由調變不同源極/汲極接面的製程參數,可進一步最佳化電晶體特性、可靠度與高頻特性。第二、穿隧式場效電晶體,利用不同源極/汲極摻雜極性的非對稱結構,實現在室溫下,元件次臨界擺幅小於理想值60 mV/dec的目的,如此可有效減低積體電路晶片可觀的耗電量,將有助於改善能源短缺問題。第三、低電壓操作的非對稱蕭基位障NOR共汲極記憶體元件,藉由只在源極端形成金屬矽化物,將傳統蕭基位障元件天生的雙極特性,巧妙的轉為單極,可以有效減低漏電流;另外,更重要的是,由於源極端的蕭基接面,將使非對稱蕭基位障NOR共汲極記憶體元件在源極端附近,比傳統NOR記憶體元件有更陡峭的位能降,故可在更低偏壓下進行資訊寫入的動作,有助於進一步記憶體元件的微縮,或是應用於鑲嵌式NOR記憶體元件。第四、無源/汲極接面的反相器。近年來,源/汲極及通道區由均勻高濃度摻雜構成的無接面場效電晶體被提出,以解決難以控制的淺且陡峭的接面難題,搭配本實驗室發展的I-line雙重微影技術,兩種無源/汲極接面的反相器在本計劃中將被發展,其中之ㄧ可省去淺溝渠隔離的面積;另一種可更進一步搭配使用共用汲極,而發展出極為節省面積的無源/汲極接面反相器。
Based on a low-cost and high-throughput I-line double patterning (DP) technology previously developed by our group, this project plans to fabricate and investigate several novel nano-scale devices featuring asymmetrical source/drain configuration, including asymmetric source/drain MOSFET, tunneling field-effective transistor (TFET), asymmetric Schottky-barrier NOR flash device, and novel inverters consisted of junctionless (J-less) transistors. While a sub-100 nm gate length can be easily achieved with the developed I-line DP methods, it is worth noting that the formation of the asymmetric source/drain in the fabricated devices is innate and feasible, and represents another inherent virtue of DP method. For NMOSFETs, this scheme provides a useful gateway to the optimization of devices’ characteristics, reliability and RF performance by means of modulating different process parameters for forming the source/drain junctions. In addition, tunneling field-effective transistor (TFET), which has the doping type of its source opposite to the drain, also lends itself nicely to the DP method. Since TFETs show the capability of breaking the limit of substhreshold swing set for conventional MOSFETs (~60 mV/dec at room temperature), in this project we also plan to fabricate TFETs with DP method to resolve the power consumption issue which plagues the conventional IC chips. In addition, in this project we’ve also proposed a novel asymmetric Schottky-barrier NOR flash device. The new device features a source-side-only Schottky junction to suppress the ambipolar characteristics and reduce the off-state leakage current inherent in the conventional Schotkky-barrier devices. As compared with conventional NOR devices, the electrons injected from the source-side-only Schottky junction are much easier to obtain sufficient energy and surmount the barrier height of oxide (3.1 eV) at the same programming conditions. It thus has a high scaling capability and great potential for embedded NOR applications. The final topic in this project is the development of two novel inverters constructed by junctionless (J-less) transistors which have uniform and heavy doping throughout the source/drain and channel regions. In this regard, two kinds of novel inverters with J-less transistors which show much better area utilization efficiency are proposed and will be developed in this project.
官方說明文件#: NSC100-2221-E009-015-MY3
URI: http://hdl.handle.net/11536/99444
https://www.grb.gov.tw/search/planDetail?id=2340430&docId=368732
Appears in Collections:Research Plans