標題: 先進之混合信號式電路設計技術開發-子計畫五:先進之靜電放電防護技術開發(I)
Development of Advanced On-Chip Esd Protection Circuits
作者: 柯明道
KER MING-DOU
國立交通大學電子工程學系及電子研究所
關鍵字: 靜電放電防護;射頻積體電路;高壓金氧半導體製程;全晶片靜電放電防護;安全操作區域;Electrostatic Discharge (ESD);Radio-Frequency Integrated Circuits (RF ICs);High-Voltage CMOS Process;Whole-Chip ESD Protection;Safe-Operating-Area (SOA).
公開日期: 2011
摘要: 在電子產品的可靠度方面,可靠度不僅影響產品良率,不良產品的使用上更有危害使用人安全之虞,電子產品的可靠度要求只會隨著晶片功能複雜度的成長而更為嚴苛,而對於電子產品中的晶片而言,靜電放電是影響其可靠度的最主要因素。在積體電路靜電放電防護中,晶片的高靜電放電耐受度,為其主要的指標,然隨著互補式金氧半導體製程技術持續進步,電晶體的各項製作參數的規格尺寸將隨之縮小,換言之,其元件耐受度亦將大幅降低,而在射頻電路的應用發展不斷提升操作頻率下,製作上需更要考量具低電容與低損耗的設計,在這些嚴刻的條件下,射頻積體電路的靜電放電防護設計,將會帶來更大的挑戰,需要有更進一步的探討和研究解決方法。另外,為了提高系統晶片的整合度,系統晶片的製作對於高壓互補式金氧半製程的需求日與劇增,但是在高壓製程中,因為製程製作複雜的影響,高壓元件本身的靜電放電防護能力偏低,為了提高系統晶片的可靠度,高壓製程的靜電放電防護能力同樣更需要進一步研究和改善。在完成積體電路相關之靜電放電防護的改善後,高壓製程的可靠度問題進一步需要針對的是安全操作區域的研究,此目標不同於高壓製程元件之靜電放電防護設計,主要在探討元件在正常工作時,電路功能操作與操作環境所帶來對於元件的影響,而根據不同的電路功能操作與操作環境調查出元件可正常運作之臨界點與界限,各臨界點所歸納出的特性曲線,即定義為安全操作區域。由於高壓製程的嚴刻操作環境,即使已經符合靜電放電規範之測試,高壓元件還必須具有穩健的安全操作區域,因此緊接在靜電放電防護設計後,加強安全操作區域將又是另一項挑戰,在高壓製程下製作的系統晶片中,高壓元件具有完善的靜電放電防護和穩健的安全操作區域範圍下,電子產品才能具備實際應用價值和競爭力。
In the electronic products, the reliability issues are very important. It will influence not only the product yield but also the user’s safety. With the function complexity increasing, the requirement of product reliability becomes stricter. However, the damage caused by electrostatic discharge (ESD) zapping is the major reliability issue in all electronic products. For the ESD protection of integrated circuits (ICs), the main demand is to achieve high ESD robustness. However, with the technology keep shrinking, devices against ESD damage are weakened. Thus, ESD protection design becomes more important to ICs in advanced CMOS processes. In the radio-frequency (RF) IC design, with the trend of operating frequency increasing, the low-capacitance and low-loss design is needed. As a result, ESD protection design for RF ICs in advanced CMOS processes will become more difficult. Therefore, it needs to further study new ESD protection methods for RF ICs.In order to increase system chips integration, the requirement of high-voltage CMOS processes is increased dramatically. But in high-voltage CMOS processes, because of complex fabrication procedure, which makes the device’s inherent ESD robustness weaker. Therefore, in order to enhance system chips robustness, ESD protection designs in high-voltage CMOS processes also need to further be studied. After enhancing the ESD protection ability of high-voltage devices, the safe operating area (SOA) is the other topic which is needed to take into consideration. This topic is different from the target of ESD protection; it studies devices behavior when devices operate under normal operating conditions. Under a high voltage and high current operating environments, the safe operating area of high-voltage devices will be suppressed. Although the chips in the product can achieve high ESD robustness, it does not mean devices will have robust safe operating area, because of the strict conditions in high-voltage operating environments. Once chips have perfect ESD protection ability and devices have robust safe operating area, the electronic products can have the useful value and competitiveness in the market.
官方說明文件#: NSC100-2221-E009-048
URI: http://hdl.handle.net/11536/99212
https://www.grb.gov.tw/search/planDetail?id=2338140&docId=368071
顯示於類別:研究計畫


文件中的檔案:

  1. 1002221E009048.PDF