標題: 超低電壓iVP之記憶體系統與智慧處理器管線設計(I)
A-Udvs Memory System Design and Intelligent Processor Pipelining for VI Sual Perception Soc
作者: 陳添福
Chen Tien-Fu
國立交通大學資訊工程學系(所)
公開日期: 2012
摘要: 低電壓的電路設計已是時勢所趨,又因製程密度的精進,低功率消耗的 IC 設計技術,必然會在往後的科技產品設計中成為不可或缺的必備功能, 然而低電壓不僅在logic cell 產生極大的延遲差異也使memory cell 的可靠度 降低。例如90nm 的製程電晶體在頻率上有將近30%的變化性,處理器及 memory system 又是SoC 設計最重要的關鍵,因此針對超低電壓SoC 之 timing variation 及memory reliability 問題的解決更是刻不容緩的任務。 本子計畫將研發於超低電壓 Intelligent Visual Perception (iVP) SoC 環境 中之記憶體系統與智慧處理器管線設計相關技術,主要目標為利用子計畫 四所提出各項低電壓SRAM/ROM 等電路技術,開發設計下列研究主題: (1) 發展處理器intelligent pipelining timing control,以達到抗變異性、 (2) 設計廣操作電壓的記憶體階層系統、與 (3) 建置系統層級超低電壓記憶體開發平台。 此子計畫將以修改 Andes N8 CPU core(已取得晶心科技RTL 授權)為主 軸,此調整處理器架構及設計廣操作電壓的記憶體將具有實質產業效益, 智慧管線設計處理器架構,使得低電壓環境下可達抗變異之效,且亦增進 處理器效能。同時我們將建構超低電壓記憶體系統開發與評估環境,加速 系統開發流程,充分支援總計畫低電壓處理器系統之整體系統開發。
With a consistent trend of low-voltage circuit techniques and process improvement, critical methodologies or techniques for low-power will play an important role in future electronic product. However, scaling to low-voltage will not only cause non-linear latency delay increasing in logic cell but also reduce reliability problems significantly in memory cell. For example, the frequency variation of transistor process achieves 30% in technology node 90nm, therefore the problems of timing variation and on-chip reliability are emergent issues in future SoC design. In the sub-project, we propose to construct three relative techniques with “A-UDVS Memory System Design and Intelligent Pipelining for Visual Sensing SoC.” First, we focus on intelligent pipelining timing control design to achieve variation-tolerant. The second “Ultra-wide-VDD-range voltage scaling memory system” is used for adaptive memory management. As well as, the third “System-level ULV system and memory hierarchy exploration environment” is for ultra-low voltage memory hierarchy development. The proposed methodology not only overcomes time variation for reliability, but also boosts up the performance by aggressively timing-stealing. Finally, in order to make the success of whole project, we plan to propose Ultra-wide-VDD-rage voltage memory system management and estimation environments.
官方說明文件#: NSC101-2221-E009-151
URI: http://hdl.handle.net/11536/98252
https://www.grb.gov.tw/search/planDetail?id=2648427&docId=399911
Appears in Collections:Research Plans