10gb/S Adaptive Cable Equalizer Using Time-Domain Approaches
|關鍵字:||接收器;等化器;斜率偵測器;過激偵測器;相位偵測器;雙二位元;receiver;equalizer;slope detector;overshoot detector;phase detector;duobinary|
|摘要:||本計畫將針對10Gb/s 銅線通訊系統應用，以標準CMOS 製程技術開發其接收
The goal of this project is to develop the adaptive equalizer in the receiver front-end for 10Gb/s cable communication applications using standard CMOS technology. Conventional frequency-domain approaches are used to build adaptive equalizers. However, the resulting small conversion gain of the power detector makes the operation of the adaptive equalizer quite sensitive to those undesired PVT variations. In this project, the time-domain techniques, such as the slope detection, overshot detection and phase detection, will be utilized to improve the reliability. Combined with our low-power and fast-locking design topology, a reliable low-power fast-locking adaptive equalizer with a wide gain tuning range can be achieved by the end of this project. For ultra-high speed applications, duobinary receiving equalizers have attracted many interests due to the corresponding relaxed requirement in channel bandwidth. However, the lack of a simple adaptive compensation mechanism becomes a major issue. It is also part of the objective of this project to develop a robust design architecture for adaptive duobinary equalizers.
|Appears in Collections:||Research Plans|