標題: On VLSI design of rank-order filtering using DCRAM architecture
作者: Lin, Meng-Chun
Dung, Lan-Rong
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: CMOS memory integrated circuits;coprocessors;image processing;median filters;nonlinear filters
公開日期: 1-Feb-2008
摘要: This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 mu m, 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 x 427.7 mu m(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8 V supply. (C) 2007 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.vlsi.2007.05.002
http://hdl.handle.net/11536/9743
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2007.05.002
期刊: INTEGRATION-THE VLSI JOURNAL
Volume: 41
Issue: 2
起始頁: 193
結束頁: 209
Appears in Collections:Articles


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