標題: Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
作者: Lin, HY
Chang, CY
Lei, TF
Liu, FM
Yang, WL
Cheng, JY
Tseng, HC
Chen, LP
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十一月-1996
摘要: A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
URI: http://dx.doi.org/10.1109/55.541762
http://hdl.handle.net/11536/971
ISSN: 0741-3106
DOI: 10.1109/55.541762
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 17
Issue: 11
起始頁: 503
結束頁: 505
顯示於類別:期刊論文


文件中的檔案:

  1. A1996VP09400003.pdf