標題: An effective decap insertion method considering power supply noise during floorplanning
作者: Lu, Chao-Hung
Chen, Hung-Ming
Liu, Chien-Nan Jimmy
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: decoupling capacitance;floorplanning;physical design;power estimation;area-array architecture
公開日期: 1-一月-2008
摘要: As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but make the power integrity problem become worse. Employing decoupling capacitances (decap) at floorplan stage has been a common approach to alleviate the supply noise problem. However, the decap budget is often overly estimated in previous researches. Besides the decap budget computation, the available floorplan space does not fully used in previous works. In one floorplan, it usually has many available spaces except the empty space that could be used to insert the decap without increasing the floorplan area. Therefore, our goal in this work is to develop a better model to calculate the required decap to solve the power supply noise problem of area-array based designs and to increase he usage of the available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results are encouraging. Compared with other approaches, our algorithm can reduce 52.6% decap budget on the MCNC benchmarks but still keep the power supply noise in the given constraint. The final floorplan areas with decap are also less than the numbers reported in previous papers.
URI: http://hdl.handle.net/11536/97
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 24
Issue: 1
起始頁: 115
結束頁: 127
顯示於類別:會議論文


文件中的檔案:

  1. 000253046500009.pdf