Title: BIST for measuring clock jitter of charge-pump phase-locked loops
Authors: Hsu, Jen-Chien
Su, Chauchin
電控工程研究所
Institute of Electrical and Control Engineering
Keywords: analog built-in self-test (BIST);jitter measurement;on-chip measurement;phase-locked loop (PLL) BIST;time-to-digital converter (TDC)
Issue Date: 1-Feb-2008
Abstract: This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.
URI: http://dx.doi.org/10.1109/TIM.2007.910109
http://hdl.handle.net/11536/9691
ISSN: 0018-9456
DOI: 10.1109/TIM.2007.910109
Journal: IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Volume: 57
Issue: 2
Begin Page: 276
End Page: 285
Appears in Collections:Articles


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