Title: An LDPC decoder chip based on self-routing network for IEEE 802.16e applications
Authors: Liu, Chih-Hao
Yen, Shau-Wei
Chen, Chih-Lung
Chang, Hsie-Chia
Lee, Chen-Yi
Hsu, Yar-Sun
Jou, Shyh-Jye
Department of Electronics Engineering and Institute of Electronics
Keywords: decoder architectures;IEEE 802.16;iterative decoders;LDPC codes;phase-overlapping;self-routing;WiMax
Issue Date: 1-Mar-2008
Abstract: An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.
URI: http://dx.doi.org/10.1109/JSSC.2007.916610
ISSN: 0018-9200
DOI: 10.1109/JSSC.2007.916610
Volume: 43
Issue: 3
Begin Page: 684
End Page: 694
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