標題: 在多重資料記憶體模組DSP架構下變數分割與指令排程方法之探討
A Study of Variable Partitioning and Instruction Scheduling Methods for DSP Architecture with Multiple Data-Memory Modules
作者: 陳正
CHEN CHENG
國立交通大學資訊工程學系
關鍵字: 數位訊號處理器 (Digital Signal Processor;DSP);多重資料記憶體模組(Multiple Data-memory Modules);指令排程 (Instruction Scheduling);迴圈平行化 (LoopParallelization);記憶體存取 (Memory Access);Digital Signal Processor (DSP);Multiple Data-memory Modules;Instruction Scheduling;Loop Parallelization;Memory Access
公開日期: 2004
摘要: 在以往數年中,我們已在國科會的資助下,針對多處理機系統及平行編譯技術二個 方面,做過較棎入的的研究,也探討過單一和多重數位訊號處理器上的指令排程法,系 統晶片架構上的靜態工作排程法,以及即時多處理機系統中具有容錯能力的動態工作排 程法。有鑑於目前在數位訊號處理器的設計領域中,為了開發潛在的記憶體頻?,提出 了包含多個資料記憶體模組的新架構,因此在本計畫中,我們將根據以往的研究經驗, 針對這種新提出的架構,探討及設計變數分割及指令排程的方法,並研製相關的模擬評 估環境。 本計畫主要提出的項目大致可分為二個方向:1. 設計指令排程法:在此架構下探討 指令排程法有二個重點,首先是定義變數分割儲存在各資料記憶體模組的機制,其次為 同時排程運算和記憶體存取指令。目前的RSVR 排程法效能不錯但在效率上仍有改善空 間,主要原因我們認為是其使用的變數分割機制不佳;因此我們定義新的變數分割機制 並設計對應的指令排程法,針對RSVR 的不足之處來做改善。另外我們也將結合 Unimodular Transformations 技術改變迴圈元素的執行順序,進一步提升我們提出方法的 效能。2. 研製相關模擬評估環境:在本計畫中我們會推導數學公式計算整體所需執行時 間,用來評估各種指令排程法的效能;但是為了縮短評估所需的時間,我們也計畫研製 相關的模擬評估環境,讓評估過程更加順利。 本計畫完成後將提供一套維謢容易且延伸性很高的模擬評估環境,並針對多重資料 記憶體模組的DSP 架構做指令排程的深入探討,以提供此方面在教學研究上一個不錯 的平台,可供業界此方面之轉移參考。
During the pass several years, we have studied thoroughly on multiprocessor system and parallel compilation techniques under support of National Science Council. We have also studied instruction scheduling methods on single/multiple Digital Signal Processor architecture, static task scheduling methods on System-on-Chip (Soc) system, and dynamic task scheduling methods with fault-tolerant ability on Real-time multiprocessor system. In order to explore higher potential memory bandwidth, multiple data-memory modules is an attractive feature for DSP architecture design. In this project, based on our experience, we will propose some effective and efficient instruction scheduling methods, and then implement the simulation and evaluation environment for this new DSP architecture. The project addresses two main issues: (1) The design of instruction scheduling methods: There are two key points for designing instruction scheduling methods on this architecture. The first one is to define the variable partition mechanism, and the second one is to schedule ALU and memory access operations simultaneously. Rotation Scheduling with Variable Repartitioning (RSVR) is an effective but not efficient enough scheduling method on this architecture, and we think its main drawback is the unfavorable variable partition mechanism. Hence, in this project, we will redefine the variable partition mechanism and propose some instruction scheduling methods to overcome its shortcomings. Besides, we also apply Unimodular Transformations technique to modify the execution sequence of iterations, which can improve the effectiveness of our proposed methods. (2) The implementation of simulation and evaluation environment: For every proposed scheduling method in this project, we will formulate their entire execution time. However, we still plan to implement a simulation and evaluation environment, which can help us evaluate our methods much easily. In summary, this project will develop a simulation and evaluation environment for DSP architecture with multiple data-memory modules, and study variable partition and instruction scheduling methods more thoroughly. It will be not only a practical environment for educational and research purposes, but also a useful tool for industrial circles. The detailed description will be given in the following contents.
官方說明文件#: NSC93-2213-E009-077
URI: http://hdl.handle.net/11536/91625
https://www.grb.gov.tw/search/planDetail?id=1007001&docId=189778
顯示於類別:研究計畫


文件中的檔案:

  1. 932213E009077.pdf