標題: 高效率智慧型面板之研究---子計畫三---整合型低操作功率元件製程設計(I)
3.3 V CMOS Self-Biased Body Poly-Si TFTs in Integrated Display(I)
作者: 冉曉雯
Zan Hsiao Wen
交通大學光電工程研究所
公開日期: 2004
摘要: 本計畫預計以三年時間,開發低操作電壓(3.3V)互補型複晶矽薄膜 電晶體製程,將利用薄膜電晶體的基板效應,和動態臨界電壓(Dynamic Threshold)電晶體之原理,設計新穎低功率自我基板偏壓複晶矽薄膜電晶體 (Self-Biased Body Poly-Si TFTs,SBB TFTs),並建立元件模型以及基本電路 模型,研究成果可結合子計畫四之顯示器週邊電路設計,發展低功率省能源 之FLC Display 驅動電路。在整合型製程方面,本計畫同時將配合子計畫二 之背光模組設計,將次波長光柵設計到TFT 陣列中,光源可以減少介面損 耗,以增加面板亮度並發展高整合性製程。 在SBB TFTs 的製作上,首先將製作作為基本測試元件的低溫複晶矽薄 膜電晶體,設計基板接觸結構,並調變通道的尺寸變化、摻雜濃度等參數。 使用不同的再結晶技術形成不同晶粒大小的複晶矽薄膜,利用電性分析技術 研究複晶矽薄膜特有之晶粒缺陷對浮動基板效應、空乏層複合產生電流和臨 界電壓的影響,整合複晶矽薄膜電晶體特殊的晶粒邊界位障主導之傳導和漏 電機制,建立一複晶矽薄膜電晶體基板效應模型。再利用PSG 薄膜或SiGe 薄膜於熱製程時於複晶矽晶粒邊界析出形成getting center 的現象,調變基板 的getting center 密度和基板累積的電壓,以降低元件臨界電壓,所製作的元 件不需要多餘的基板連接,更由於基板效應可使元件臨界電壓大幅降低,從 而改善元件驅動能力。最後,研究所製作之N 型及P 型SBB TFTs 之可靠度, 同時製作互補型反相器,完成基本元件操作的物理模型,並建立穩定並可配 合電路設計需求調變的製程規格,實現低功率高驅動能力之複晶矽薄膜電晶 體製程開發。 在高整合性製程的開發上,本計畫將研發相容的製程,配合e-beam 將 次波長光柵整合到元件閘極製作中,改善FLC 面板的亮度。
The goal of this project is to develop low-operation-voltage (3.3 V) CMOS poly-Si thin film transistor (TFT) fabrication process in three years. We are going to design novel low-power self-biased body (SBB) poly-Si TFTs and establish device and basic circuit modals utilizing the principle of body effect and dynamic threshold of MOSFETs. The research results can be used to develop low-power and energy-saving driving circuits for FLC displays in combination with the display peripheral circuit design from the sub-project 4. For the integration of the fabrication process, we will include the sub-wavelength grating obtained from the backlight system design of the sub-project 2 into the TFT array so that brightness can be increased and fabrication process can be highly integrated. We will start by fabricating low-temperature poly-Si (LTPS) TFTs as the basic test devices. Then we will design body contact structures and change parameters such as the channel sizes and doping concentrations. Utilization of different re-crystallization techniques to form poly-Si thin films with different grain sizes, analysis the influence of inter- and intra-grain defects in poly-Si thin films on the floating body effect, the threshold voltage, and the recombination/generation currents of the drain depleting region by using electrical characterization techniques, and integration of the conduction and leakage mechanisms caused by grain boundary barriers of poly-Si TFTs will all contribute to the establishment of a model for poly-Si TFT body effect. With adequate thermal process, PSG or SiGe thin film will be used to serve as the getting center layer under device channel. Then the body voltage will be modulated by the trapped charge in getting center layer, accordingly adjust the threshold voltage of the SBB devices. Finally, the CMOS SBB TFT process will be developed by combining NTFT and PTFT together. Optimal process window will be delivered while analyzing CMOS SBB TFT inverter characteristics. As a result, the high performance, low power-consumption CMOS TFT circuitry can be developed for the application in sub-project 4. To enhance the integration ability of the Smart Display, our project also tries to include the sub-wavelength grating into the TFT array by cooperating with sub-project 2. Then, the interface scattering effect of light source can be minimized and consequently the luminescence can be further enhanced.
官方說明文件#: NSC93-2215-E009-074
URI: http://hdl.handle.net/11536/91404
https://www.grb.gov.tw/search/planDetail?id=1047889&docId=199797
顯示於類別:研究計畫


文件中的檔案:

  1. 932215E009074.pdf