Title: A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques
Authors: Huang, Chun-Cheng
Wang, Chung-Yi
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Analog-digital conversion;calibration;clocks;comparators;flash ADC;offset;time-interleaved ADC;time interleaving;timing circuits;timing skew
Issue Date: 1-Apr-2011
Abstract: An 8-channel 6-bit 16-GS/s time-interleaved analog-to-digital converter (TI ADC) was fabricated using a 65 nm CMOS technology. Each analog-to-digital channel is a 6-bit flash ADC. Its comparators are latches without the preamplifiers. The input-referred offsets of the latches are reduced by digital offset calibration. The TI ADC includes a multi-phase clock generator that uses a delay-locked loop to generate 8 sampling clocks from a reference clock of the same frequency. The uniformity of the sampling intervals is ensured by digital timing-skew calibration. Both the offset calibration and the timing-skew calibration run continuously in the background. At 16 GS/s sampling rate, this ADC chip achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The chip consumes 435 mW from a 1.5 V supply. The ADC active area is 0.93 x 1.58 mm(2).
URI: http://dx.doi.org/10.1109/JSSC.2011.2109511
http://hdl.handle.net/11536/9084
ISSN: 0018-9200
DOI: 10.1109/JSSC.2011.2109511
Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 46
Issue: 4
Begin Page: 848
End Page: 858
Appears in Collections:Articles


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