標題: Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels
作者: Su, Chun-Jung
Tsai, Tzu-I
Liou, Yu-Ling
Lin, Zer-Ming
Lin, Horng-Chih
Chao, Tien-Sheng
電子物理學系
電子工程學系及電子研究所
奈米中心
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
Nano Facility Center
關鍵字: Accumulation mode;gate all around (GAA);inversion mode (IM);nanowire (NW);thin-film transistor (TFT)
公開日期: 1-四月-2011
摘要: In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
URI: http://dx.doi.org/10.1109/LED.2011.2107498
http://hdl.handle.net/11536/9075
ISSN: 0741-3106
DOI: 10.1109/LED.2011.2107498
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 32
Issue: 4
起始頁: 521
結束頁: 523
顯示於類別:期刊論文


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  1. 000288664800031.pdf