Title: Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels
Authors: Su, Chun-Jung
Tsai, Tzu-I
Liou, Yu-Ling
Lin, Zer-Ming
Lin, Horng-Chih
Chao, Tien-Sheng
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
Nano Facility Center
Keywords: Accumulation mode;gate all around (GAA);inversion mode (IM);nanowire (NW);thin-film transistor (TFT)
Issue Date: 1-Apr-2011
Abstract: In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
URI: http://dx.doi.org/10.1109/LED.2011.2107498
ISSN: 0741-3106
DOI: 10.1109/LED.2011.2107498
Volume: 32
Issue: 4
Begin Page: 521
End Page: 523
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