Title: Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
Authors: Huang, Juinn-Dar
Chen, Chia-I
Lin, Yen-Ting
Hsu, Wan-Ling
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: communication synthesis;distributed register-file microarchitecture;interconnect minimization;resource binding;scheduling
Issue Date: 1-Apr-2011
Abstract: In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that tip to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.
URI: http://dx.doi.org/10.1587/transfun.E94.A.1151
http://hdl.handle.net/11536/9026
ISSN: 0916-8508
DOI: 10.1587/transfun.E94.A.1151
Journal: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume: E94A
Issue: 4
Begin Page: 1151
End Page: 1155
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