標題: Suppression of boron penetration in BF2+-implanted poly-Si gate
作者: Chao, TS
Chu, CH
Wang, CF
Ho, KJ
Lei, TF
Lee, CL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: boron;penetration;stack poly-Si;N2O oxide
公開日期: 1-十二月-1996
摘要: In this paper, a comprehensive study of gate engineering to suppress the penetration of boron in p-type metaloxide-semiconductor held-effect transistor (MOSFET) with the p(+)-poly-Si-gate is reported. Four types of poly-Si gate structure, two types of gate dielectrics were investigated to suppress the boron penetration. Among the different gate structures, the stacked amorphous silicon structure was found to be the most effective way to retard the boron penetration. N2O oxide exhibited a better retarding of the boron diffusion as compared with the O-2 oxide. It was found that a combination of stacked amorphous silicon with N2O oxide is the most effective way to suppress the boron penetration. Thermal stability, oxide integrity, and D-it of this sample are superior to all the other samples.
URI: http://dx.doi.org/10.1143/JJAP.35.6003
http://hdl.handle.net/11536/901
ISSN: 0021-4922
DOI: 10.1143/JJAP.35.6003
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
Volume: 35
Issue: 12A
起始頁: 6003
結束頁: 6007
顯示於類別:期刊論文


文件中的檔案:

  1. A1996WF47900017.pdf