Development of Advanced Nano-scale MOSFETs with Asymmetrical Source/Drain
|關鍵字:||非對稱蕭特基薄膜電晶體;雙重微影技術;鎳矽化合物;Asymmetric Schottky-barrier (ASSB);double patterning technique;NiSi|
Based on a low-cost and high-throughput I-line double patterning (DP) technology previously developed by our group, this project plans to fabricate and investigate several novel nano-scale devices featuring asymmetrical source/drain configuration, including asymmetric source/drain MOSFET, tunneling field-effective transistor (TFET), asymmetric Schottky-barrier NOR flash device, and novel inverters consisted of junctionless (J-less) transistors. While a sub-100 nm gate length can be easily achieved with the developed I-line DP methods, it is worth noting that the formation of the asymmetric source/drain in the fabricated devices is innate and feasible, and represents another inherent virtue of DP method. For NMOSFETs, this scheme provides a useful gateway to the optimization of devices’ characteristics, reliability and RF performance by means of modulating different process parameters for forming the source/drain junctions. In addition, tunneling field-effective transistor (TFET), which has the doping type of its source opposite to the drain, also lends itself nicely to the DP method. Since TFETs show the capability of breaking the limit of substhreshold swing set for conventional MOSFETs (~60 mV/dec at room temperature), in this project we also plan to fabricate TFETs with DP method to resolve the power consumption issue which plagues the conventional IC chips. In addition, in this project we’ve also proposed a novel asymmetric Schottky-barrier NOR flash device. The new device features a source-side-only Schottky junction to suppress the ambipolar characteristics and reduce the off-state leakage current inherent in the conventional Schotkky-barrier devices. As compared with conventional NOR devices, the electrons injected from the source-side-only Schottky junction are much easier to obtain sufficient energy and surmount the barrier height of oxide (3.1 eV) at the same programming conditions. It thus has a high scaling capability and great potential for embedded NOR applications. The final topic in this project is the development of two novel inverters constructed by junctionless (J-less) transistors which have uniform and heavy doping throughout the source/drain and channel regions. In this regard, two kinds of novel inverters with J-less transistors which show much better area utilization efficiency are proposed and will be developed in this project.