標題: Low-temperature characteristics of well-type guard rings in epitaxial CMOS
作者: Huang, CY
Chen, MJ
Jeng, JK
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十二月-1996
摘要: Characterization and simulation of minority-carrier well-type guard rings in epitaxial substrate at 77 K were performed and compared with those at RT, The escape probability in a narrow guard-ring structure under the same amount of minority carrier injection increases by about one order of magnitude when temperature decreases to 77 K, This degradation in the guard-ring efficiency can be attributed to the enhanced drift mechanism in the conductivity-modulated layer between the well bottom junction and the epitaxial high/low junction at 77 K, In contrast, this mechanism enhances the width dependence of the escape probability at 77 K. The higher minority-carrier recombination velocity of the epitaxial high-low junction contributes to the stronger width dependence secondarily, When the epitaxial layer thickness becomes thinner, the simulation also demonstrates a stronger width dependence of the escape current as well as reduction in its magnitude, A lightly-doped epitaxial layer on a heavily-doped substrate exhibits even more importance in the guard ring efficiency for low temperature operation, and its thickness should be kept as thin as possible.
URI: http://dx.doi.org/10.1109/16.544418
http://hdl.handle.net/11536/899
ISSN: 0018-9383
DOI: 10.1109/16.544418
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 43
Issue: 12
起始頁: 2249
結束頁: 2260
顯示於類別:期刊論文


文件中的檔案:

  1. A1996VU87900027.pdf