標題: A high-performance thin-film transistor with a vertical offset structure
作者: Chang, CY
Lin, CW
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十二月-1996
摘要: In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (mu c-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT), This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFT's with a much higher drivability. The fabrication process is simple, low temperature (less than or equal to 300 degrees C), and low cost, with a potential for high reliability.
URI: http://dx.doi.org/10.1109/55.545774
http://hdl.handle.net/11536/891
ISSN: 0741-3106
DOI: 10.1109/55.545774
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 17
Issue: 12
起始頁: 572
結束頁: 574
顯示於類別:期刊論文


文件中的檔案:

  1. A1996VX16300009.pdf