標題: Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications
作者: Lin, Tay-Jyi
Chen, Shin-Kai
Kuo, Yu-Ting
Liu, Chih-Wei
Hsiao, Pi-Chen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: VLIW;digital signal processor;register organization;instruction encoding;micro-architecture
公開日期: 1-Jun-2008
摘要: This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1 similar to 26.0%. The DSP has been fabricated in the UMC 0.13 mu m 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 x 3.15 mm(2) including 160 KB on-chip SRAM.
URI: http://dx.doi.org/10.1007/s11265-007-0061-x
http://hdl.handle.net/11536/8757
ISSN: 1939-8018
DOI: 10.1007/s11265-007-0061-x
期刊: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Volume: 51
Issue: 3
起始頁: 209
結束頁: 223
Appears in Collections:Articles


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