標題: Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
作者: Lin, Chin-Teng
Yu, Yuan-Chu
Van, Lan-Da
資訊工程學系
電機學院
電控工程研究所
Department of Computer Science
College of Electrical and Computer Engineering
Institute of Electrical and Control Engineering
關鍵字: computation complexity;cost effective;hardware utilization;next-generation wireless communications;pipeline architecture;R4(2)SDF;triple modes
公開日期: 1-八月-2008
摘要: This investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.
URI: http://dx.doi.org/10.1109/TVLSI.2008.2000676
http://hdl.handle.net/11536/8532
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2008.2000676
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 16
Issue: 8
起始頁: 1058
結束頁: 1071
顯示於類別:期刊論文


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  1. 000257987400011.pdf