標題: The Linear Combination Model for the Degradation of Amorphous Silicon Thin Film Transistors under Drain AC Stress
作者: Tai, Ya Hsiang
Tsai, Ming-Hsien
Huang, Shih-Che
工學院
光電工程學系
顯示科技研究所
College of Engineering
Department of Photonics
Institute of Display
關鍵字: a-Si:H thin film transistor (TFT);drain stress;reliability model
公開日期: 1-Aug-2008
摘要: The degradation behavior of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) under steady-state (DC) and pulsed (AC) stress on drain electrode has been investigated in this paper. Signals with various peak levels, frequencies and duty ratios are applied onto the drain electrode to see their effects on device's reliability. The effects of state creation and removal are found to still be the dominant degradation mechanisms of drain stress. With the experiment data, it is significantly proved that the degradation behavior can be predicted by analyzing the gate-to-source and gate-to-drain vertical electric field during stress. Furthermore. a linear combination model has been contributed in this paper. By using this model, one can estimate the threshold volta, e shift under drain AC stress of different voltage levels, frequencies, duty ratios for a given stress time. With satisfactory agreement between the real and estimated data, this model has been proved to be very useful in predicting and evaluating a-Si:H TFT reliability with both gate and drain signal applied.
URI: http://dx.doi.org/10.1143/JJAP.47.6228
http://hdl.handle.net/11536/8503
ISSN: 0021-4922
DOI: 10.1143/JJAP.47.6228
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS
Volume: 47
Issue: 8
起始頁: 6228
結束頁: 6235
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