標題: Efficient hierarchical motion estimation algorithm and its VLSI architecture
作者: Wu, Bing-Fei
Peng, Hsin-Yuan
Yu, Tung-Lung
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: hierarchical;motion estimation;multiresolution;VLSI
公開日期: 1-Oct-2008
摘要: This paper addresses the development and hardware implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiresolution frames to reduce the computational complexity. Excellent estimation performance is ensured using an averaging filter to downsample the original image. At the smallest resolution, the least two motion vector candidates are selected using a full-search block matching algorithm. At the middle level, these two candidate motion vectors are employed as the center points for small range local searches. Then, at the original resolution, the final motion vector is obtained by performing a local search around the single candidate from the middle level. HMEA exhibits regular data flow and is suitable for hardware implementation. An efficient VLSI architecture that includes an averaging filter to downsample the image and two 2-D semisystolic processing element arrays to determine the sum of absolute difference in pipeline is also presented. Simulation results indicate that HMEA is more area-efficient and faster than many full-search and multiresolution architectures while maintaining high video quality. This architecture with 59K gates and 1393 bytes of RAM is implemented for a search range of [-16.0, +15.5].
URI: http://dx.doi.org/10.1109/TVLSI.2008.2000526
http://hdl.handle.net/11536/8316
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2008.2000526
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 16
Issue: 10
起始頁: 1385
結束頁: 1398
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