標題: Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET
作者: Liu, Po-Tsun
Huang, Chen-Shuo
Lim, Peng-Soon
Lee, Da-Yuan
Tsao, Shueh-Wen
Chen, Chi-Chun
Tao, Hun-Jan
Mii, Yuh-Jier
光電工程學系
顯示科技研究所
Department of Photonics
Institute of Display
關鍵字: Gate leakage current;MOSFETs;stress memorization technique (SMT)
公開日期: 1-Nov-2008
摘要: Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.
URI: http://dx.doi.org/10.1109/LED.2008.2005518
http://hdl.handle.net/11536/8195
ISSN: 0741-3106
DOI: 10.1109/LED.2008.2005518
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 29
Issue: 11
起始頁: 1249
結束頁: 1251
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