Title: A novel planarization of oxide-filled shallow-trench isolation
Authors: Cheng, JY
Lei, TF
Chao, TS
Yen, DLW
Lin, CJ
電子工程學系及電子研究所
奈米中心
Department of Electronics Engineering and Institute of Electronics
Nano Facility Center
Issue Date: 1-Jan-1997
Abstract: Two planarization approaches of the oxide-filled trench isolation have been evaluated. Results show that the oxide-filled shallow-trench isolation technology based on a chemical-mechanical polishing (CMP) process is difficult to control and has a poor uniformity. It also results in a dishing effect in wide field regions. On the other hand, a new planarization process can achieve an excellent uniformity and fully planar surface by using a combination of a masking polysilicon layer based on a CMP process, selective wet etching for oxide refill on active regions, short-time CMP process for oxide refill, and reactive ion etching etchback. Results also show that the high breakdown yield of the gate oxide and the low leakage current of the n(+)/p junction diodes with the novel planarization process demonstrates extremely low defect density from this process. This new process is a very promising candidate for oxide-filled shallow-trench isolation.
URI: http://hdl.handle.net/11536/817
ISSN: 0013-4651
Journal: JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume: 144
Issue: 1
Begin Page: 315
End Page: 320
Appears in Collections:Articles


Files in This Item:

  1. A1997WG07000051.pdf