標題: 應用於超寬頻脈衝通訊系統之接收機前端電路設計與實現
A Front-End Receiver Design and Implementation for Impulse Radio Ultra-Wideband Communication Systems
作者: 謝明憲
Ming-Hsien Hsieh
陳富強
Fu-Chiarng Chen
電信工程研究所
關鍵字: 超寬頻;脈衝;同調性;低雜訊放大器;變壓器回授;相關器;脈波產生器;Ultra-Wideband;Impulse Radio;Coherence;Low Noise Amplifier;Transformer Feedback;Correlator;Pulse Generator
公開日期: 2007
摘要: 在本論文研究中,將針對脈衝超寬頻的低功率、低複雜度架構之特性,設計出適用於脈衝超寬頻通訊系統之接收機前端電路。首先各別設計低雜訊放大器及相關器。低雜訊放大器方面採用變壓器作輸入匹配,由於反向變壓器之電感隨著頻率增加而變小,經小訊號模型推導後發現可將此特性應用在寬頻匹配上。另外在增益級部分運用電流再利用技巧達到低功耗、高增益之特性。經量測後得到在3.1~10.6GHz輸入反射損耗S11<-9.8dB,平均順向增益S21=11.2dB,且頻帶內變異為1.2dB。最低雜訊表現為3.2dB。另外相關器是作為訊號偵測及解調之用,此次以吉伯特架構作時域訊號相乘,並以電感產生零點作頻寬的延伸,再加上可調增益之機制。實際量測得到輸出振幅為36-89mV,與模擬之可調範圍有些許差距。最後我們整合前端電路在單一晶片上,其子電路包含低雜訊放大器、脈波產生器以及類比相關器三個子電路。首先雙極性之開關式二階微分高斯脈波產生器,經模擬後得到脈波寬度約為260ps。而相關器有別於之前設計,此次乘法器是以四相位架構實現,目的是將接收後經放大的訊號與脈波產生器產生當作本地訊號作相乘,並經過在差動輸出端加上的跨接電容以完成積分,另外再串一級運算放大器,加上主極點消除技術以延伸頻寬,由於此技術所用之電容橫跨在運算放大器的輸入輸出級上,同樣亦具有積分效果。整個接收電路經量測後適用在110Mbps或更高之傳輸速率上,上升時間約為1.8ns,持續時間為2.2ns。此高傳輸以及低功耗等特性證明可應用在超寬頻脈衝通訊系統上。
In this thesis we focus on the characteristics of low power, low complex architecture and design of a front-end receiver used in IR-UWB communication systems. First of all, the LNA and correlator are designed separately. The wideband input matching of LNA is realized by the transformer feedback topology instead of multi-stage filters. Since the inductance of the inverting transformer degrades as frequency increases, this characteristic can be applied in wideband matching by means of small-signal model. As to gain stage, the current-reuse technique reduces power dissipation and obtains adequate gain simultaneously. The measured results in 3.1 to 10.6 GHz show that S11 is less than -9.8 dB, S21 is equal to 11.2 dB with 1.2 dB variation, the minimum NF is 3.2 dB. Further, the correlator used for detecting signal is realized by the Gilbert multiplier. Some mechanisms are developed for bandwidth extension and dynamic gain control. The practical measurement shows that the output amplitude is 36-89mV. The adjustable range is slightly different from that in simulation. Finally, the integrated front-end receiver is proposed. The single chip comprises three sub-blocks including a wideband LNA, a pulse generator, and an analog correlator. The bi-phase, switched, 2nd derivative pulse generator can generate the pulse width of 260ps. The analog correlator is modified and different from the previous design. It utilizes a four-quadrant multiplier and integral capacitors to implement the design. Besides, we exploit zero-pole cancelling topology to reach bandwidth enhancement and doubly integration simultaneously. The whole front-end receiver can work functionally in 110Mb/s, and the rise time and hold time of the demodulated signal are about 1.8ns and 2.2ns, respectively. The features prove that it is suitable in IR-UWB communication systems.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009413617
http://hdl.handle.net/11536/80877
Appears in Collections:Thesis


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