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dc.contributor.author黃昱瑞en_US
dc.contributor.authorYu-Ruei Huangen_US
dc.contributor.author趙學永en_US
dc.contributor.author溫瓌岸en_US
dc.contributor.authorHsueh-Yung Chaoen_US
dc.contributor.authorKuei-Ann Wenen_US
dc.date.accessioned2014-12-12T03:04:16Z-
dc.date.available2014-12-12T03:04:16Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009413613en_US
dc.identifier.urihttp://hdl.handle.net/11536/80873-
dc.description.abstract本論文提出一個利用除二電路放置在混頻器的下一級的方式,有效的抑制頻率合成器中頻帶內的突波雜訊。並完成利用UWB頻率 3.1-GHz到6.3-GHz作為測試平台的頻率合成器,突波雜訊將產生在頻帶外於欲得到載波頻率兩倍的地方。因此,可與其他操作在2.5-GHz及5.2-GHz頻段的無線區城網路共同存在。其他突波雜訊抑制的技術,例如:在選頻器上加上dummy-pair,或是LC共振腔內加上可調式的負電阻,都被運用在此工作內來降低雜訊。此外,並完成利用單一頻率源合成出UWB所有的頻帶且突波雜訊在所有的頻帶可被壓制在-25dBc以下。本電路利用聯電0.13製程技術完成。zh_TW
dc.description.abstractThis thesis presents a CMOS frequency synthesizer with an efficient algorithm for in-band spurious suppression by using the divide-by-two circuit after the mixer. An implementation example had been developed with UWB Synthesizer from 3.1-GHz to 6.3-GHz as the test bench. The spurious are introduced at the twice of the desired carrier frequencies and out of the band. Therefore, it allows to co-existence with WLAN applications operating in 2.5-GHz ISM and 5.2-GHz ISM. Other spurious suppressing techniques, such as selector with dummy pairs and LC resonant loads with tunable negative resistance, are also used in this work to help degrade the undesired tons. Furthermore, a single frequency source is adopted to generate all the bands specified by UWB and the spurious suppression is better than -25dBc in all band groups. The circuits are designed by UMC 0.13-μm CMOS.en_US
dc.language.isoen_USen_US
dc.subject頻率合感器zh_TW
dc.subject突波雜訊zh_TW
dc.subjectsynthesizeren_US
dc.subjectspuriousen_US
dc.title應用於UWB頻率合成器之突波雜訊抑制設計zh_TW
dc.titleSpurious Suppressing Design for UWB Synthesizersen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
Appears in Collections:Thesis


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