標題: 互補式金氧半積體電路之系統層級靜電放電防護設計
System-Level ESD Protection Design in CMOS ICs With Transient Detection Circuits
作者: 顏承正
Yen, Cheng-Cheng
柯明道
Ker, Ming-Dou
電子研究所
關鍵字: 靜電放電;系統層級靜電放電測試;快速暫態脈衝測試;偵測電路;轉換器;Electrostatic Discharge (ESD);System-Level ESD Test;Electrical Fast Transient (EFT) Test;Detection Circuit;Converter
公開日期: 2008
摘要: 在互補式金氧半積體電路中,系統層級靜電放電測試(System-Level ESD Test)已成為一個重要的可靠度問題。由於日益複雜的積體電路功能,如混合式信號(Mix-Signal)電路、多重電源供應系統(Multiple Power Supplies)、射頻(Radio Frequency, RF)電路、系統單晶片(System on Chip)等等,使得積體電路元件所處的環境會受到來自元件內部或外部的雜訊干擾,因此這些雜訊會隨機地出現在積體電路產品的電源、接地、輸入/輸出腳位(Pin)上,使積體電路產品較以往更容易受到雜訊干擾的威脅。隨著半導體元件尺寸的微縮,過去的研究已經證實在系統層級靜電放電測試以及快速暫態脈衝測試(Electrical Fast Transient Test)之下,暫態的干擾訊號會使寄生在互補式金氧半導體積體電路中的矽控整流器(Silicon ControlledRectifier, SCR)產生閂鎖效應。由系統層級靜電放電測試所引起的可靠度問題來自於多功能整合型的積體電路設計,以及嚴格的法規要求。在系統層級靜電放電測試的規格中(IEC 61000-4-2),一個擁有積體電路的電子設備在接觸放電(Contact-Discharge)及空氣放電(Air-Discharge)測試模式中如欲達到“等級四"的標準需求,則此待測設備(Equipment Under Test, EUT)必須通過高達±8kV(接觸放電模式)及±15kV(空氣放電模式)的靜電放電等級需求。 在傳統的解決方法中,會在電子產品的印刷電路板上增加離散元件(Discrete Component)抑制暫態雜訊的干擾,包括利用反耦合電容(Decoupling Capacitor)、Ferrite Choke、暫態突波抑制器(Transient Voltage Suppressor)、限流電阻(Current-Limiting Resistance)、防護板(Shielding Plate)等,皆能在印刷電路板抑制對積體電路產品所產生的暫態雜訊干擾,但是這些額外增加的離散元件會大幅增加電子產品的成本。因此在以積體電路方式提出相關的解決方案,設計出符合高階系統層級靜電放電測試規格以及減少離散元件使用的電子產品,將會為工業界所急切需求。 有鑒於此,本論文將針對用於系統層級靜電放電防護所需的暫態偵測電路積體電路設計進行研究分析。主要的研究方向包括:(1) 評估不同電源匯流排之間的靜電放電箝制電路(Power-Rail ESD Clamp Circuit)結構對於系統層級靜電放電測試的耐受度,(2) 在快速脈衝測試時暫態觸發閂鎖效應的物理機制,(3) 評估各種面板層級(Board-Level)雜訊濾波器對抑制暫態觸發閂鎖效應的效用,(4) 暫態偵測電路積體電路設計方法(IC Design Methodology),以及(5) 暫態數位轉換器積體電路設計方法。 本論文第二章首先評估不同電源匯流排之間的靜電放電箝制電路(Power-Rail ESD Clamp Circuit)結構對於系統層級靜電放電測試以及快速暫態脈衝測試的耐受度。在本論文中,發現在電源匯流排之間的靜電放電箝制電路結構中具有鎖存迴授迴路以及串接PMOS迴授迴路電路架構容易產生似閉鎖效應(Latchup-Like Failure)之故障出現,在系統層級靜電放電以及快速暫態脈衝測試過後,在電源(VDD)與地端(VSS)之間導致巨大電流通過,容易使積體電路產品因過大電流而損毀。相較於以三級反相器為主的靜電放電箝制電路架構,該具有鎖存迴授迴路以及串接PMOS迴授迴路的電源匯流排之間的靜電放電箝制電路架構較易發生類似閂鎖效應(Latchup-Like Failure)之故障狀況。本論文中提出一個結合鎖存迴授迴路以及利用NMOS產生回復功能的新電源匯流排之間的靜電放電箝制電路結構,經實驗晶片驗證,本研究所提出的電源匯流排間靜電放電箝制電路結構可成功避免類似閂鎖效應的觸發,以及具有高箝制能力且能節省佈局面積,可應用在全晶片之靜電放電防護設計上。 本論文第三章針對在快速暫態脈衝測試時造成暫態觸發閂鎖效應的物理機制加以探討分析。經由相關的實驗量測驗証,本論文發現快速暫態脈衝測試將導致一種電壓振幅會隨時間遞減的脈衝震盪電壓產生於積體電路的電源腳位上。此種電壓會使儲存於積體電路內的少數載子(Minority Carrier)快速移動,進一步形成“掃回電流(Sweep-Back Current)”而引發暫態觸發閂鎖效應。本論文所提出的實驗驗證提供實用的研究分析工具,以期能進一步發展出能有效防止暫態觸發閂鎖效應的電路設計技巧、佈局(Layout)準則、以及半導體製程技術。為了能更進一步地提升積體電路對暫態觸發閂鎖效應的防護能力,本論文更評估了不同面板層級雜訊濾波器對抑制暫態觸發閂鎖效應的實際效用。這些雜訊濾波元件包括電容濾波器、電容-電感濾波器(LC-Like)、□形濾波器、亞鐵鹽珠(Ferrite Bead)、暫態突波抑制器(Transient Voltage Suppressor, TVS)、及混合式濾波器等。藉由這些雜訊濾波元件反耦合(Decouple)或吸收因快速暫態脈衝測試在積體電路電源(地)端造成的瞬間雜訊,則積體電路對抑制暫態觸發閂鎖效應的防護能力將可有效提升。所得到的實驗結果可提供印刷電路板(Printed Circuit Board, PCB)設計者一個有用的參考準則,以期能利用適當的雜訊濾波器來有效提升積體電路對暫態觸發閂鎖效應的防護能力。 本論文第四章是在0.18-um 3.3-V CMOS製程技術中,所實現的暫態偵測電路(Transient detection Circuit)。此偵測電路是利用閉鎖電路的架構來設計,利用HSPICE軟體所提供的正弦波以及阻尼因子(Damping Factor)的參數設定,可成功模擬並量化暫態偵測電路在系統層級靜電放電以及快速暫態脈衝測試時的工作情形。電路系統的模擬狀態包括了在電源線與地線上的同步干擾,或因為電路板繞線差異或待測元件擺放位置不同而造成在電源線與地線之間的非同步干擾情形,以及在各種不同製程參數下對於暫態偵測電路的影響。此暫態偵測電路在系統層級靜電放電或是快速暫態脈衝發生時,可偵測出發生在電源線上的暫態干擾訊號並紀錄之,並配合韌體或軟體設定,使電路在受到電磁干擾而故障時,能送出重新啟動訊號(Reset)使系統自動作回復的動作。此暫態偵測電路可整合至CMOS晶片中,並可結合韌體的使用,以提升待測電子產品對系統層級靜電放電以及快速暫態脈衝測試的防護能力。 本論文第五章是在0.18-um 1.8-V CMOS製程技術中,所實現的暫態偵測電路。此偵測電路是利用反相器電路架構以及電阻電容延遲效應來設計,利用HSPICE軟體所提供的正弦波以及阻尼因子(Damping Factor)的參數設定,可成功模擬並量化此暫態偵測電路在系統層級靜電放電以及快速暫態脈衝測試時的工作情形。此暫態偵測電路在系統層級靜電放電或是快速暫態脈衝發生時,已成功驗證可偵測出發生在電源線上的暫態干擾訊號並紀錄之,使電子產品在受到電磁干擾而故障時,可配合韌體或軟體設定送出重新啟動訊號(Reset)使系統自動作回復的動作。 本論文第六章是結合暫態偵測電路以及積體電路濾波電路(On-Chip Noise Filter Network),發展完全整合於積體電路上(Full Integrated Circuit)能輸出數位編碼訊號的暫態數位轉換器(Transient-to-Digital Converter)。在系統層級靜電放電測試時,暫態數位轉換器所輸出的數位編碼訊號會對應不同電壓準位的暫態突波。在整體系統的設計上,利用結合韌體(Firmware)的系統設計,制定出具有執行自動恢復功能的整體系統規劃。當有快速變化且具有低電壓準位的暫態突波發生時,暫態數位轉換器會送出低位元數位編碼訊號,可做為韌體執行部分系統自動重新恢復(Partial System Auto-Recovery)的指標(Index),指標訊號可暫存於韌體中,並經由回授程式的不斷檢測,直至暫態突波的影響消失為止。當有快速變化且具有低電壓準位的暫態突波發生時,暫態數位轉換器會送出高位元數位編碼訊號,可做為韌體執行全部系統自動重新恢復(Total System Auto-Recovery)的指標。因此,利用結合暫態數位轉換器以及韌體的系統規劃的設計方式,以期增進顯示電子產品對系統規格靜電放電的全晶片防護能力。 以上針對用於系統層級靜電放電測試的積體電路設計方法,快速暫態脈衝測試造成的暫態閂鎖效應特性,以及暫態偵測電路晶片設計,本論文所進行的相關研究皆有實際晶片量測,並有相對應的國際會議及期刊論文發表
System-level electrostatic discharge (ESD) events have become a primary reliability issue in CMOS integrated circuit (IC) products. With more and more complicated design of integrated circuits, such as mixed-signal, mixed-voltage, system-on-chip (SOC), etc, CMOS devices will suffer more electrical transient noises coming from environment and the interior of CMOS ICs. With advanced semiconductor technology of scaled clearance between PMOS and NMOS devices, it has been proven that such electrical transient noises can cause transient-induced latchup (TLU) failure on the inevitable parasitic silicon controlled rectifier (SCR) in CMOS ICs under system-level ESD and electrical fast transient (EFT) tests. The reliability issue of system-level ESD events results from not only the progress of more integrated functions into a single chip but also from the strict requirements of reliability test standards, such as the system-level ESD test standard of IEC 61000-4-2. The microelectronic products must sustain the ESD level of ±8kV (±15kV) under contact-discharge (air-discharge) test mode to achieve the immunity requirement of “level 4” in the IEC 61000-4-2 test standard. The additional noise filter networks, such as the magnetic core, capacitor filter, ferrite bead (FB), transient voltage suppressor (TVS), RC filters, are often used to improve the system-level ESD immunity of microelectronic products. The system-level ESD immunity of CMOS ICs under system-level ESD test can be significantly enhanced by choosing proper noise filter networks. However, the additional discrete noise-bypassing components substantially increase the total cost of microelectronic products. Therefore, the chip-level solutions to meet high system-level ESD specification for microelectronic products without additional discrete noise-decoupling components on the microelectronic products are highly desired by IC industry. This dissertation focuses on the chip-level solutions for the system-level ESD protection design. Several major topics including: (1) investigation on the latchup-like failure of power-rail ESD clamp circuits under system-level ESD tests, (2) clarification of TLU physical mechanism under EFT tests, (3) evaluations of board-level noise filters to suppress TLU, (3) proposed on-chip transient detection circuits, and (5) proposed transient-to-digital converters. In chapter 2, four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-um CMOS process and tested to compare their system-level ESD and EFT susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD and EFT tests, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a “latch-on” state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD and EFT tests. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD and EFT tests. In chapter 3, the occurrence of TLU in CMOS ICs under the EFT tests is studied. The test chip with the parasitic SCR structure fabricated by a 0.18-um CMOS process was used in the EFT tests. For physical mechanism characterization, the specific “sweep-back” current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved. In chapter 4, a novel RC-based on-chip transient detection circuit for system-level ESD and EFT protection are proposed in this work. The circuit performance to detect positive and negative electrical transients under system-level ESD and EFT testing conditions has been investigated by the HSPICE simulation and verified in silicon chip. The experimental results have confirmed that the proposed on-chip transient detection circuit can successfully memorize the occurrence of the system-level ESD and EFT events. The detection output of proposed on-chip transient detection circuits can be used as the firmware index to execute system recovery procedure to provide a hardware/firmware co-design to improve the immunity of CMOS IC products against electrical transient disturbance. In chapter 5, a new on-chip transient detection circuit for electrical fast disturbance protection design is proposed in this work. The circuit performance to detect different positive and negative ESD-induced or EFT-induced transient disturbance has been investigated by the HSPICE simulation and verified in silicon chip. The EFT generator combined with attenuation network and capacitive coupling clamp has been used as the evaluation method to verify the detection function of the proposed on-chip transient detection circuit under EFT tests. The test chip in a 0.18-um CMOS process with 1.8-V devices has confirmed that the proposed on-chip transient detection circuit can successfully detect and memorize the occurrence of the transient disturbance under system-level ESD or EFT tests. In chapter 6, a novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18-um CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. These output digital codes can be used as the firmware index to execute different auto-recovery procedures in microelectronic systems. Thus, the proposed on-chip transient-to-digital converter can be further combined with firmware design to provide an effective solution to solve the system-level ESD and EFT protection issue in microelectronic systems equipped with CMOS ICs. Chapter 7 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009011846
http://hdl.handle.net/11536/80803
Appears in Collections:Thesis


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