標題: 可變超取樣率三角積分類比數位轉換器之低面積降頻器電路設計與實現
Design and implementation of a small area decimator for programmable oversampling ratio sigma-delta A/D converters
作者: 唐江俊
Chiang-Chun Tang
闕河鳴
Herming Chiueh
電信工程研究所
關鍵字: 降頻器;三角積分類比數位轉換器;decimator;sigma-delta
公開日期: 2008
摘要: 在很多領域,三角積分類比數位轉換器近來非常受歡迎。而三角積分類比數位轉換器主要由類比電路(三角積分調變器)和數位電路(降頻器)所構成。然而,數位電路部分佔據了整個三角積分類比數位轉換器的絕大多數積體電路面積。而且對於可變超取樣率的三角積分類比數位轉換器而言,需要不同頻寬的數位濾波器去取出所要的訊號頻段,這樣的需求也會導致額外的數位電路面積消耗。 在此,一個針對可變超取樣率三角積分類比數位轉換器的低面積降頻器被設計與實現。而最主要的改良是在於裡頭的高階有限脈衝響應濾波器。對於調換結構並採用多相分解的有限脈衝響應濾波器,可藉由使用摺疊和儲存元件共享技巧,並且在此主要配合使用特別的控制電路去改變計算程序以重複使用儲存元件來達到降低面積的目的。在此提出的電路架構,與廣泛採用的直接結構摺疊架構相比,由於只需使用一半的儲存元件,因此可得到較小的電路面積。此外,在此提出的架構不因節省面積而對電路的其他特性有所損傷,也就是本架構除了面積較小外,關鍵路徑也較短,等待週期也較少並且尖峰功率消耗也較小(平均功率在相同的水平)。 由於只需使用一半的儲存元件,本架構相對於直接結構摺疊架構而言,可使降頻器裡的高階有限脈衝響應濾波器減少24.6%的矽面積,進而達到整體使用四個階段降頻器15.8%的面積節省(對於三個階段降頻器,整體面積則可減少20.9%)。
The sigma-delta modulation (SDM) has become a very popular analog to digital conversion technique in many fields. A sigma–delta A/D converter consists of analog circuits (sigma–delta modulator, SDM) and digital circuits (decimator). However, the silicon area of sigma-delta A/D converters is governed largely by the digital parts. Moreover, the distinct bandwidth digital lowpass filters are required to perform selecting-signal for programmable oversampling ratio SDM, which results in extra filters hardware consumption in digital part of SDM A/D converters. The small area decimator for programmable oversampling ratio SDM A/D converters is designed and implemented. The main improvement in this thesis is focused on the high order FIR filter of decimator. Combing the folding and the storage elements sharing techniques for decimation FIR filters using polyphase decomposition in transposed-form as well as changing the computation procedures mainly to reuse storage elements by using extra control circuits, the area reduction compared with the widely used folded FIR filter architecture in direct-form is obtained due to half storage elements (registers) requirement. In addition, the extra advantages of my proposed folded decimation FIR filter architecture based on transposed-form are shorter critical path, smaller peak power (average power in the same level), and shorter latency. As a result of half registers requirement, the 24.6% area reduction for high order (126th-order) FIR filter is obtained, which result in 15.8% area reduction for the 4-stages decimator (20.9% area reduction for 3-stages decimator).
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009413535
http://hdl.handle.net/11536/80798
Appears in Collections:Thesis


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