標題: 用於管線式類比數位轉換器之數位背景校正技術
Digital Background Calibration of Pipelined ADCs
作者: 范振麟
Fan, Jen-Lin
吳介琮
Wu, Jieh-Tsorng
電子研究所
關鍵字: 管線式類比數位轉換器;背景校正技術;類比數位轉換;Pipelioned ADC;Background Calibration;analog-to-digital conversion
公開日期: 2008
摘要: 隨著先進製程的進步,MOS電晶體的通道長度越來越短,電晶體的寄生效應也因此隨之變 小,這樣可以大大提升其操作速度以及節省功率消耗。但是因為通道長度的縮短,也使 得電晶體的輸出阻抗降低;另外因為越來越薄的oxide厚度,為了元件的可靠度,工作電 壓也隨之下降。因為輸出阻抗變小與工作電壓的降低,使得類比電路設計難以得到高增 益以及大動態範圍的要求。這些因素都使得類比電路設計的難度越來越高,讓類比電路 的效能面臨嚴峻的考驗。\\ 電壓式的切換電容管線式類比數位轉換器目前被廣泛的使用,因為其在運作時將一個高 增益的運算放大器操作在負迴授的狀態,使得其轉換特性可以達到高線性度以及高準確 度的要求,但是因為的電容不匹配或者是有限增益的運算放大器會在類比數位轉換器的 輸出造成非線性的失真。以目前CMOS的製程技術,電容的匹配可以讓類比數位轉換器達 到10-12Bit 左右的解析度;但是先進製程卻使得要設計一個高增益放大器的難度變得相 當的高,既使達到增益的設計要求,但是卻往往會犧牲運算放大器的操作速度。所以如 何利用一個高速低增益的運算放大器,設計出一個高效能的類比數位轉換器,是本篇論 文的重點。\\ 本篇論文描述一個應用於管線式類比數位轉換器之強健背景校正技術。對於一個切換電 容式的管線式類比數位轉換器,我們可以切割他的輸入取樣電容,並且將亂數序列利用 切割的電容混入主要的訊號之中。輸入的亂數序列可以利用類比數位轉換器的輸出加以 萃取出來,如此便可以不影響到類比數位轉換器的正常工作達到校正的目的。利用與數 入相關的亂數產生序列,就可以使得類比數位轉換器的工作不需要額外的輸出擺幅。\\ 我們實現了一個65奈米金氧半場效電晶體製程的12-Bit、80~MHz、32mW之管線式類比數 位轉換器,它利用新的背景校正技術,將類比數位轉換器所造成的非線性加以校正,其 中除了將增益以及次數位類比轉換器加以校正之外,更進一步將運算放大器之非線性增 益所造成之非線性失真加以修正。我們所提出的技術是強健而且不會受到元件不匹配的 影響,另外也不需額外的輸出擺幅。因為我們減輕類比電路所需要的準確度與線性度要 求,所以可以利用比較簡單並且省電的方式來實現類比電路。我們實現的類比數位轉換 器在輸入為2~MHz的弦波,並且工作在80MS/s時可以達到67~dB的SNDR與81~dB的SFDR。\\ 另外我們還提出一個切割通道的類比數位轉換器架構來減少校正所需要的時間。這個切 割通道類比數位轉換器,由兩個一樣的類比數位轉換器所組成,它們接收相同的輸入訊 號,但是利用不同的亂數序列來進行校正。我們在校正資料萃取前將兩個類比數位轉換 器的輸出加以比較並且將雜訊先加以消除,如此便可以大幅降低所需要的校正時間。在 此篇論文之中我們將所提出的架構利用理論分析與系統模擬加以驗證。
Following the progress of advanced technology, the channel length of MOS transistor is smaller and the parasitic is also reduced. These characteristics make the transistor be able to be operated in higher frequency and lower power dissipation. However, the output impedance of MOS transistor reduces with the channel length. In addition to the output impedance, the thickness of gate oxide also becomes thinner than a long channel device. For device reliability issue, supply voltage scales down with channel length. The reduced output impedance and supply voltage make analog circuits can not be designed with high gain and large dynamic range. These features make the design of high performance analog circuits more difficult.\\ Voltage-mode switched-capacitor (SC) pipelined ADC is widely used. This circuit is operated with high gain operation amp (opamp) and configures in negative feedback. The negative feedback circuit can achieve high linearity and high accuracy at the same time. However, with capacitor mismatch and finite opamp's dc gain, the output of a pipelined ADC may contain servere nonlinearity. The capacitor matching with present CMOS technology can be used to design a pipelined ADC with 10-12 bit resolution. But it's hard to design a high gain opamp with high unit-gain frequency in deep-submicron technology. The main purpose of this thesis is to design a high performance pipelined ADC in deep-submicron technology.\\ This thesis presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust. For a SC pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC's signal path, and then calibration data can be extracted from the ADC's digital output without interrupting its normal conversion operation. Using an input-dependent scheme to generate the calibration random sequence, no additional signal range is required to accommodate the extra calibration signal.\\ A 32-mW 12-bit 80-MS/s pipelined ADC was fabricated using a 65~nm CMOS technology. The ADC demonstrates a new digital background technique, which corrects pipeline stage nonlinearity as well as gain and sub-DAC errors. The proposed technique is robust and immune to device mismatches, and does not need extra signal range. Since the accuracy and linearity requirements are mitigated, analog circuits with less complexity and power can be used. The ADC achieves 67~dB SNDR and 81~dB SFDR at 80~MS/s sampling rate with a 2~MHz sinewave input. \\ In addition, a split-channel ADC architecture is proposed to reduce the calibration time. The split-channel ADC consists of two A/D channels that receive the same analog input but employ different random sequences for calibration. The calibration time can be greatly reduced by comparing the digital outputs from both channels and then removing the embedded perturbations before extracting the calibration data. The proposed calibration techniques are analyzed by using both theoretical formulation and system-level simulation.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009011836
http://hdl.handle.net/11536/80758
Appears in Collections:Thesis


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