標題: 可程式化展頻時脈產生器
Programmable Spread Spectrum Clock Generator
作者: 程議賢
YiSian Cheng
蘇朝琴
ChauChin Su
電控工程研究所
關鍵字: 鎖相迴路;非整數頻率合成器;展頻時脈產生器;三角積分調變器;phase-locked loop;fractional-N frequency synthesizer;spread spectrum clock generator;sigma-delta modulator
公開日期: 2007
摘要: 在電子系統中,伴隨著高頻時脈的需要帶來了嚴重的電磁干擾(EMI)效應。而近年來如展頻時脈技術的發展已經能有效地解決這問題。 本論文提出一個可程式化展頻時脈產生器。它是利用三角積分調變器(sigma-delta modulator)的非整數頻率合成(fractional-N)技術來設計,且達到一三角波調變的展頻功能。此外,在時脈展頻上它可以產生調變頻率從30 khz至300 khz之間變化; 展頻比例從2500 ppm至50000 ppm之間變化。 可程式化展頻時脈產生器是使用台積電 0.13 um 1P8M RF 製程來實現。經模擬結果顯示非展頻情況下的時脈抖動為5.6 ps;功率消耗為18毫瓦;晶片面積約為750um*750um。而各個時脈展頻皆達到我們所期許的展頻行為。
In electronic systems, along with a high frequency of clock often comes series electromagnetic interference (EMI) effects. A technique, referred to as spread spectrum clock generation, is recently proposed to solve effectively. In this thesis, we propose a programmable spread spectrum clock generator (SSCG). It is based on the fractional-N technique using the sigma-delta modulator. The programmable SSCG achieves the spread spectrum function with triangular waveform modulation. In addition, it generates the clock with the various modulation frequencies from 30 kHz to 300 kHz and the various spread ratios from 2500 ppm to 50000 ppm. The programmable SSCG is implemented in TSMC 0.13 um 1P8M RF technology. The simulation results show that the non spreading clock has a peak-to-peak jitter of 5.6 ps, the power dissipation is 18 mW and the chip size is 750um*750um. This architecture does achieve various spread spectrum profiles as expected.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009412584
http://hdl.handle.net/11536/80718
Appears in Collections:Thesis


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  1. 258401.pdf