A study on the Metal Gate Materials and Technology for the CMOS Application
|關鍵字:||金屬閘極;互補式電晶體;功函數;metal gate;CMOS;work function|
|摘要:||互補式金氧半電晶體(CMOS)進化至45奈米技術後，多晶矽閘極將遭遇其物理限制–多晶矽空乏、硼穿透和高電阻係數，尋找多晶矽閘極替代物變得更為迫切，解決這些物理限制，金屬閘極是一明確的選擇。整合金屬閘極於互補式金氧半電晶體將帶來新的挑戰，金屬閘極的採用需要提供元件有更好的效能與令人滿意的可靠度且金屬閘極須有適當的有效功函數(work function)使元件有適當的起始電壓(threshold voltage)，本論文中，吾人將探討數種金屬閘極材料區分為金屬氮化物，二元金屬合金與全金屬矽化閘極。
其次，另一耐火金屬鎢經氮化後調變有效功函數，氮化鎢含氮元素高於原子百分比44其晶相為WN且此晶相穩定度高達800 oC，縱使氮濃度高達原子百分比61，並無更高晶相產生。氮化鎢中過多的氮元素在溫度低於766 oC便會析出，且過多的氮會導致氮化鎢有效功函數下降，在氧化鉿上會有輕微的費米栓效應，這種情形下，氮化鎢可應用於p-型全空乏絕緣層上矽(SOI)金氧半場效電晶體元件，但不適合當塊材(bulk) p-型金氧半場效電晶體閘極。
金屬氮化物的高阻值迫使吾人思考堆疊(stack)結構當閘極，探討銅/氮化鉭(Cu/TaNx)堆疊，其中低電阻值層(銅層)適合當主要的導電材料，底層(氮化鉭層)用以當起始電壓控制材料。氮化鉭中氮含量原子百分比為23-39，且薄膜幾乎為非晶結構，熱穩定度高達800 oC，氮化鉭的有效功函數約為4.31-4.38 eV，氮成分調變有效功函數能力低於70 meV，元件平帶電壓均值隨著溫度增高而下降且平帶電壓標準差增大，雖然在高溫時晶相變化、晶粒成長與銅污染會貢獻平帶電壓不穩定性，在600 oC熱應力致氧化層電荷主導平帶電壓下降與標準差，銅/氮化鉭堆疊閘極可使用於n-型金氧半場效電晶體銅/氮化鉭，其製程最高溫度需控制在500 oC.
雖然金屬氮化物具高溫熱穩定性，但其有效功函數範圍並不夠大，吾人展示一種有效的功函數調變方法，利用二元金屬合金而非金屬半化物，選擇適當的金屬成分與組成，可獲得任意功函數之二元金屬合金。調變鉭基材合金(鉭-鈦和鉭-鉑)其有效功函數可連續分部於4.16-5.2 eV， 如此大範圍功函數使得該金屬合金適用於互補式金氧半場效電晶體，鉭與鉑經混合後，其核心電子束縛能改變，佐證合金功函數可依金屬合金系統調整，而且鉭膜中混合鉑元素會造成結晶變差且形成合金晶相，經參透式電子顯微鏡確認鉭-鉑合金薄膜中晶粒為奈米尺寸。
最後，一種新方法(雜質植入矽化物)用以實現全金屬矽化閘極有效功函數調變，全金屬矽化閘極容易整合於傳統金氧半場效電晶體製程，且利用雜質推積於全矽化物與底層絕緣材料介面，擁有大範圍的有效功函數調變。半導體矽經全金屬矽化後，植入BF+與P+雜質接著作退火可有效調變全金屬矽化閘極功函數。但當底層絕緣層材料為氧化鉿，會產生費米栓效應，限制功函數調變，一層薄的二氧化矽介面層可減緩費米栓效應。雖然矽化鎳全矽化閘極在二氧化矽尚可穩定到600 oC，但長時間處於600 oC，熱應力與雜質擴散會導致氧化層劣化，全矽化後製程溫度建議低於500 oC以緩和氧化層劣化。
As the evolution of the CMOS technology beyond the 45 nm technology node, poly-silicon gate encounters several inherent limitations – poly-Si depletion, boron penetration, and high resistivity. It becomes urgent to seek replacements for the poly-silicon gate. Metal gate is an obvious choice to solve all of the limitations. However, to integrate metal gates with CMOS process faces new process challenges. The introduction of metal gates should provide devices better performance and competent reliability, and the metal gates should have proper work functions to make devices meet suitable threshold voltages. In this dissertation, several metal gate materials including metal nitrides, binary metal alloys, and fully silicided gates were investigatred. The MoNx gates were studied at first. The main phase of the MoNx films with the 46 – 59 at. % of nitrogen is MoN. As the N/Mo ratio increases, the microstructure of MoNx film tends to be amorphous-like and the resistivity increases. The work function of MoNx increases with the increase of nitrogen content and tends to saturate at the valence band of Si. No Fermi-level pinning effect is observed on HfO2 film. These results indicate that MoN is a good candidate of gate electrode for PMOSFETs. The WNx films with nitrogen higher than 44 % atomic ratio has a main phase of WN, and the WN phase is stable up to 800 □C. The higher order WNx phase does not form even if the nitrogen concentration is as high as 61%. The excess nitrogen atoms in WNx films desorbs at temperatures below 766 □C. The excess nitrogen in WNx films can cause the effective work function lowering. Weak Fermi-level pinning effect is observed on HfO2 film. In this case, WNx/HfO2 gate stack can be applied to p-type fully-depletion SOI devices but WNx is not suitable to be meal gate of bulk p-type MOSFTEs. The high resistance of metal nitride forces us to consider the stack structure as gate electrodes. We investigate the Cu/TaNx stack of witch the Cu layer serves as the major conduction material and the TaNx layer serves as the threshold voltage control material. As the nitrogen content of TaNx varies in the range 23 – 39 at. %, TaNx films are almost amorphous and are thermally stable up to 800 ℃. The work function of TaNx is about 4.31-4.38 eV and the modulation range is less than 70meV. The mean value of flatband voltage decreases and the deviation of the flatband voltage increases with the increase of the annealing temperature. Although phase change, grain growth, and Cu contamination contribute the instability of flat band voltage at high temperature, thermal stress-induced oxide charges dominate these thermal instability at 600 ℃. The Therefore, Cu/TaNx stack gate electrode can be used for the nMOSFETs, and the maximum process temperature following gate electrode deposition should be 500 ℃. Although metal nitrides are thermally stable, the work function modulation range is not large enough. We demonstrate an effective method of work function modulation by the binary metal alloys instead of metal nitrides. Any work function can be obtained by the binary metallic alloy system with a proper composition of high and low work function metals. Binding energies of core level electrons of Ta and Pt change due to the intermixing of Ta and Pt, which is the mechanism that work function of alloys are adjusted in the metallic alloy systems. The work function of the Ta-based metal alloys (Ta-Ti and Ta-Pt) can be modulated from 4.16 eV to 5.2 eV continuously. Such a wide range work function modulation makes them suitable for CMOS applications. Moreover, incorporation of Pt in Ta film induces poor crystallization and a compound phase of Ta-Pt alloys. Transmission electron microscopy analysis confirmed that grain sizes of Ta-Pt alloys were nano-scale. Finally, a new method, implant-to-silicide (ITS), is used to realize effective work function (Φm,eff) adjustments of fully silicided (FUSI) gates. FUSI gate is easily to integrate with the conventional CMOS process and have a wide range modulation of effective work function by impurities pile-up at the interface between silicide and gate dielectric. The Φm,eff of NiSi FUSI gates on SiO2 can be tuned by incorporating BF2+ or P+ dopants after silicidation. Nevertheless, the Fermi-level pinning effect is observed in the NiSi/HfO2 gate which limits the Φm,eff adjustment. A thin SiO2 interfacial layer between HfO2 and FUSI gates can reduce the Fermi-level pinning effect. A NiSi FUSI gate on SiO2 is thermally stable up to 600 °C. The thermal stress and impurity diffusion after a prolonged 600 °C annealing degrade the oxide integrity. The temperature of the post-silicidation process should be as low as 500 oC. In summary, the small work function range of single metal nitrides restricts that the metal nitrides can only been used for the dual metal scheme. Although the metallic alloys reveal wide range of work function, the integration of different composition of metallic alloys in CMOS application is difficult by the single metal process. Fully silicided gates doped by the N-type and P-type impurities are the most promising process for the single metal dual work function scheme. However, the interaction between poly-Si and high-k materials before silicidation induces Fermi-level pinning and will retard the application of fully silicided gates. Up to date, there are still no perfect choice of metal gate materials and processes. The standard metal gates for the CMOS are still under consideration to the dual metal scheme or fully silicided gates.
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