標題: 全金屬矽化物互補式金氧半製程之矽控整流器及其在射頻電路之靜電放電防護設計與應用
SCR-Based ESD Protection Designs for Radio-Frequency Integrated Circuits in Fully Silicided CMOS Process
作者: 林群祐
Lin, Chun-Yu
柯明道
Ker, Ming-Dou
電子研究所
關鍵字: 靜電放電防護設計;矽控整流器;射頻積體電路;ESD Protection Design;Silicon-Controlled Rectifier;Radio-Frequency Integrated Circuit
公開日期: 2008
摘要:   在所有積體電路產品中,皆必須於量產時符合可靠度 (Reliability) 的規範,以提供該積體電路產品足夠的耐用年限。而隨著奈米級互補式金氧半製程的持續發展,靜電放電 (Electrostatic Discharge, ESD) 防護已成為積體電路產品可靠度中相當艱鉅的挑戰,大多數電子產品的故障與損壞均與遭受靜電放電轟擊有關。為避免積體電路遭受靜電放電的威脅與破壞,所有積體電路與外界接觸的銲墊 (Pad) 皆須搭配靜電放電防護設計。   無線通訊裝置中的射頻 (Radio Frequency, RF) 電路,因其連接射頻收發機與外接之濾波器或天線,因此亦需搭配靜電放電防護設計。由於射頻電路操作在數十億赫茲 (Gigahertz, GHz) 以上的工作頻率,如此高頻的工作頻率對於訊號路徑上的寄生效應有極為極嚴格的限制,靜電放電防護電路的寄生效應必須達到最小化的設計,以避免射頻電路性能的嚴重衰減。在寄生效應嚴格限制的情況下,矽控整流器 (Silicon-Controlled Rectifier, SCR) 是極為有用的靜電放電防護元件。由於在二極體 (Diode)、矽控整流器、雙載子電晶體 (BJT)、金氧半場效電晶體 (MOSFET)、或者是場氧化層電晶體 (Field Oxide Device, FOD) 等眾多的靜電放電防護元件中,矽控整流器具有面積最小、寄生效應最小、靜電放電耐受度最好的優點,並且完全相容於一般互補式金氧半製程的步驟,不需額外的光罩去遮蔽金屬矽化物 (Silicide Blocking),尤其將它應用在先進製程中不會有閂鎖效應 (Latchup) 的問題,因此可以廣泛應用在積體電路中當作靜電放電防護元件。然而過高的觸發電壓與較慢的導通速度,使得矽控整流器在實際應用上必須搭配有效地低電壓觸發與高效率導通之設計。矽控整流器基本特性是由電流觸發而導通的元件,所以當有一觸發電流施加於矽控整流器的基體時,矽控整流器便可很快地經由正回授再生機制 (Positive-Feedback Regeneration Mechanism) 觸發進入導通狀態。   搭配矽控整流器的射頻電路之靜電放電防護設計是本論文的研究主題,本論文的章節包括:(1) 使用交叉耦合 (Cross Couple) 的矽控整流器之差動式低雜訊放大器 (Low-Noise Amplifier, LNA) 設計、(2) 超低寄生電容的矽控整流器設計、(3) 搭配超低寄生電容的矽控整流器之超寬頻功率放大器 (Power Amplifier, PA)、(4) 應用在射頻電路與靜電放電防護電路共同設計之寄生電容模型、(5) 利用矽控整流器設計之可耐高工作電壓以及低漏電之靜電放電箝制電路。   本論文第二章針對一種射頻窄頻前端電路與靜電放電防護電路共同設計。本章使用 130 奈米互補式金氧半製程設計一個工作於 5 GHz 的差動式低雜訊放大器,並探討差動式低雜訊放大器接點對接點 (Pin to Pin) 之靜電放電耐受度。新提出的靜電放電防護設計於兩個差動輸入銲墊間使用交叉耦合的矽控整流器,除了可提供單一輸入銲墊至電源線與接地線的靜電放電防護外,更可提供兩個差動輸入銲墊間的接點對接點模式靜電放電防護功能。此設計的人體放電模式 (Human Body Model, HBM) 與機械放電模式 (Machine-Model, MM) 靜電放電耐受度分別為 3.5 kV 與 300 V。相關的射頻性能以及靜電放電耐受度皆於第二章內比較與討論。   第三章藉由改變矽控整流器的元件佈局方式以降低寄生效應。在矽控整流器中使用方塊狀 (Waffle) 之新型佈局結構,可在相同晶片佈局面積下提供最大靜電放電路徑周長,因此可在最小寄生電容的前提下,提供最高的靜電放電防護能力。換句話說,方塊狀之矽控整流器可降低元件本身的寄生電容值。本研究於 0.18 微米互補式金氧半製程中實現此新型設計,並且不需增加元件和其他成本,故十分適合應用於射頻電路之靜電放電防護設計。   利用新提出之方塊狀矽控整流器,第四章將其應用於射頻功率放大器之靜電放電防護電路。本章使用 130 奈米互補式金氧半製程實現此射頻電路,實驗證明此靜電放電防護策略可有效地提供防護等級超過 8-kV 人體放電模式之靜電放電轟擊測試、與 800-V 機械放電模式之靜電放電轟擊測試。實驗結果亦證明,靜電放電轟擊確實對射頻功率放大器的射頻操作效能有極大的影響,射頻功率放大器極需靜電放電防護設計,否則無法於靜電放電轟擊下存活。   隨著射頻電路工作頻率持續升高,靜電放電防護電路的寄生效應也愈來愈難以掌握,因此,需要將電路中所使用的元件模型建立起來,才能更有效地控制靜電放電防護電路的寄生特性。本論文第五章建立起矽控整流器在高頻操作時的元件模型,以便利用射頻電路與靜電放電防護電路共同設計的方式,設計出具有良好射頻效能以及優異靜電放電防護能力的射頻積體電路。除了靜電放電防護元件以外,銲墊也會在訊號路徑上對射頻訊號造成負面影響。本章針對一種具有低電容值的銲墊進行研究,利用其等效電路模型進一步提出低損耗 (Loss) 設計,並於 65 奈米互補式金氧半製程中實現此設計。實驗結果顯示,銲墊的等效電容可於特定頻段內大幅降低,同時訊號損耗也可降低,因此可避免影響射頻電路之性能。   電源箝制靜電放電防護電路 (Power-Rail ESD Clamp Circuit) 是達成積體電路產品全晶片靜電放電防護極為重要的設計,本論文第六章提出了新型的可耐高工作電壓以及低漏電之靜電放電箝制電路。本章使用 65 奈米互補式金氧半製程實作,在此可耐高工作電壓之靜電放電箝制電路中,所有電晶體都是利用低壓元件來實現,可以安全地偏壓在兩倍工作電壓下而不會有閘極氧化層的可靠度問題,並且不需使用低漏電製程即可達成降低漏電的目標。由實驗結果可知,此電路擁有極高的靜電放電能力,而且在正常操作的情況下只有 100-nA 等級的漏電流,因此,本靜電放電箝制電路十分適合應用在系統單晶片 (System-on-a-Chip, SoC) 之混合電壓輸入輸出界面 (Mixed-Voltage I/O Interfaces)。   第七章總結本論文的研究成果,並提出數個接續本論文研究方向的研究題目。本論文所提出的各項新型設計,皆已搭配實驗晶片加以驗證。此外,本研究有數篇國際期刊與國際研討會論文發表,並有數項創新設計已提出中華民國及美國專利申請。
In order to be safely used and provide moderate life time, all microelectronic products must meet the reliability specifications during mass production. Electrostatic discharge (ESD), which was one of the most important reliability issues in the integrated circuit (IC), must be taken into consideration during the design phase of all IC products. All pads which connect the IC and the external world, including the input/output (I/O) pads, VDD pads, and VSS pads, need to be equipped with ESD protection circuits to provide effective ESD protection for the IC. Since the radio-frequency (RF) front-end circuits in wireless communication devices connect the RF transceiver to the external antenna or band-select filter, they must need ESD protections. However, the ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path. For the RF front-end circuits operating in the frequency band from several gigahertzes to tens of gigahertz, they have the strict limitations of the parasitic effects on the signal path in such high operating frequency. This situation leads to the challenge in ESD protection design for RF circuits, which is to achieve the highest ESD robustness with the smallest performance degradation. In other words, the parasitic effects of the ESD protection devices need to be minimized. Moreover, the evolution of CMOS process increases the difficulty of ESD protection design. As CMOS process is continuously scaled down, the power-supply voltage is decreased and the gate oxide becomes thinner, which leads to the reduced gate-oxide breakdown voltage of MOS transistor. However, ESD was not scaled down with the CMOS technology, so the MOS transistors with thinner gate oxide are more vulnerable to ESD. The aforementioned design challenges form the motivation of this dissertation. The research topics of this dissertation including: (1) ESD protection design on a 5-GHz differential low-noise amplifier with cross-coupled SCR, (2) optimization on SCR device with low capacitance for RF ESD protections, (3) ESD protection design on an ultra-wideband power amplifier with waffle-structured SCR, (4) modeling parasitic capacitance for matching network co-designed in RF ICs, and (5) high-voltage-tolerant ESD clamp circuit by using only low-voltage devices with low standby leakage in nanoscale CMOS process. In chapter 2, the pin-to-pin ESD protection design on a 5-GHz differential LNA is proposed. The 5-GHz differential LNA is implemented in a 130-nm CMOS process. The new ESD protection scheme for differential input pads is realized with the cross-coupled SCR. This ESD protection scheme achieves 3.5-kV HBM and 300-V MM ESD levels, respectively. SCR realized in waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance in chapter 3. The proposed waffle-structured SCR has been verified in a 0.18-µm CMOS process. The waffle layout structure of SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with waffle layout structure and its turn-on time has also been investigated in silicon chip. In chapter 4, the waffle-structured SCR is applied to an ultra-wideband (UWB) RF power amplifier (PA). The waffle-structured SCR is designed with ESD detection and trigger circuit to provide the best ESD protection capability while contributing minimum parasitic capacitance to the RF PA in a 130-nm CMOS process. The measurement results have verified the effectiveness of the proposed ESD protection strategy and proved that this ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 800V MM ESD level. As the operating frequencies of RF front-end circuits are increased, on-chip ESD protection designs for RF applications are more challenging, and they should be designed more carefully. In chapter 5, the small-signal circuit model of waffle-structured SCR has been presented and proved in silicon. The measured parasitic capacitances well agree with the simulated capacitances. The RF circuits can be well co-designed with the presented small-signal model to eliminate the negative impacts from ESD protection SCR on RF performances. Besides, the optimized design of the bond pad for RF applications was also investigated. The experimental results in a 65-nm CMOS process have proven that the bond pad capacitance and insertion loss can be successfully reduced by the optimized bond pad structure. The small-signal circuit model of the optimized bond pad has also been presented for RF circuit designs. The efficient power-rail ESD clamp circuit must be included into the RF ICs to reduce the dimensions of ESD devices connected to the I/O pad. In chapter 6, the new 2×VDD-tolerant ESD clamp circuit by using only low-voltage devices with low standby leakage current and high ESD robustness for system-on-a-chip (SoC) applications with mixed-voltage I/O interfaces has been successfully designed and verified in a 65-nm CMOS process. The 2×VDD-tolerant ESD clamp circuit can operate without gate-oxide reliability issue, and the leakage current is only in the order of 100 nA under normal circuit operating condition. Besides, there is no latchup concern in this design. The new ESD clamp circuit by using only low-voltage devices with very low standby leakage current and high ESD robustness is the useful circuit solution for on-chip ESD protection design with mixed-voltage I/O interfaces in SoC applications. In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of the fabricated test chips have demonstrated the performance improvement. The achievements of this dissertation have been published or submitted to several international journal and conference papers. Several innovative designs have been applied for patents.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411709
http://hdl.handle.net/11536/80620
Appears in Collections:Thesis


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