標題: A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
作者: Ker, MD
Chang, HH
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge;ESD protection circuit;gate-couple technique;low-voltage-triggered lateral SCR;PMOS-triggered lateral SCR;NMOS-triggered lateral SCR;human-body model;machine model;charged device model;ESD-implant process
公開日期: 1-一月-1997
摘要: A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding an extra ESD-implant mask, Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress, The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor, Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS IC's can be fully protected against ESD damage, Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.
URI: http://hdl.handle.net/11536/806
ISSN: 0018-9200
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 32
Issue: 1
起始頁: 38
結束頁: 51
顯示於類別:期刊論文


文件中的檔案:

  1. A1997WA65300006.pdf