標題: 氮化矽快閃式記憶元件可靠度之探討
Investigation of Reliability Issues in Nitride Trap Storage Flash Memory
作者: 古紹泓
Shaw-Hung Gu
汪大暉
Tahui Wang
電子研究所
關鍵字: 氮化矽快閃式記憶元件;耐久性;電荷幫浦量測;寫入電荷水平分佈;抹除狀態臨界電壓不穩定;讀取擾動;SONOS-type trapping storage flash memories;Endurance;Charge pumping technique;Programmed charge lateral distribution;Erase-Vt state threshold voltage instability;Read-disturb
公開日期: 2006
摘要: 本篇論文主要著重在研究以氮化矽(SiN)為電荷儲存之快閃式記憶元件可靠性議題(reliability issue)研究。一般而言,為了增加電荷保存能力(retentivity),此元件通常選用較厚的底部氧化層(bottom oxide)。元件在未加壓之前,其具有相當優異的可靠度。然而,當經過多次寫入/抹除(program/erase)後,會使得氧化層造成傷害,進而對元件可靠性造成極大的影響。 第一章簡介此元件基本的結構以及寫入抹除的方式。對於二位元操作時反向讀取(reverse reading)的原理,也詳列於其中。第二章探討元件耐久性(endurance)機制。吾人發現,無論在寫入或抹除狀態之臨界電壓準位,皆會隨著寫入/抹除次數的增加而皆有向上揚升的現象。 第三章詳述一改良後之電荷幫浦(charge pumping)量測方法。藉由此法,在汲極/源極接面上之寫入電荷水平分佈,可獨立被萃取出來。吾人研究發現,在同一元件中,第二寫入的位元有著比第一寫入位元較寬的電荷分佈。此原因為在寫入第二位元時,第一寫入位元產生的電場會加速通道電子使其提早注入氮化矽層中。另外,實驗結果顯示,寫入電荷分佈會隨著寫入抹除次數增加而延伸到通道中央。 第四章中,吾人對抹除狀態臨界電壓不穩定(threshold voltage instability)、讀取擾動(read-disturb),以及寫入狀態資料流失(charge loss)有著深入的探討。首先,對於一經加壓後的元件,抹除狀態之臨界電壓會隨著儲存時間而上升。此漂移現象與溫度有著微弱的關係並且隨寫入抹除次數呈現奇特的轉彎現象(turn-around),這與底部氧化層中帶正電性缺陷的生成有著密切關係。吾人實驗結果發現,此臨界電壓漂移與時間呈現對數(logarithm)的相依性,並可用穿隧波前(tunneling front)模型來做描述。此外,若是讀取偏壓太大,正電性電荷幫助穿隧(PCAT)效應將會主導臨界電壓漂移,與時間將會轉變成指數(power-law)關係。藉由研究垂直電場以及溫度對氮化矽層電荷遺失之影響,吾人提出一解析之物理模型:Frenkel-Poole蒸散進而透過氧化層缺陷穿隧。吾人可利用此模型提出一閘極偏壓加速測試元件資料保存時間之方法。 第五章探討底部氧化層厚度以及加壓效應對於氮化矽記憶元件資料流失的影響。根據多電子捕捉(multiple electron trapping)模型,吾人利用一數值分析方法,分別對底部氧化層厚度為1.8nm到5.0nm的元件模擬其電荷保存特性。在吾人的模型中,假設氮化矽中缺陷為連續性的分佈。傳導帶(conduction band)與氮化矽中缺陷狀態(trap state)的暫態行為,可用一連串Frenkel-Poole激發以及電子再度被捕陷(re-capture)來描述。電荷流失可分為兩種途徑:一是傳導帶電子透過正電性氧化層缺陷而流失;二是電子直接穿隧過底部氧化層而散失。透過大面積元件量測,吾人發現在較厚的底部氧化層元件中,經由加壓後引致的電荷逸失現象呈現兩階段(two stages)發展。第一階段電荷漏電流被氧化層缺陷幫助穿隧給限制住。第二階段中,因Frenkel-Poole散失使其而遵循1/t的時間關係。從第一階段到第二階段之間的過渡時間與氧化層缺陷幫助穿隧時間有關,但是將會被延長一個特定比例。基於以上的了解,吾人在第六章中,利用此1/t暫態電流,萃取出氮化矽材料中缺陷的密度。 第七章中,吾人針對一局部儲存(localized storage)、多準位(multi-level)氮化矽快閃式記憶元件中,因寫入/抹除加壓後產生隨機電報雜訊(random telegraph noise, RTN)導致之讀取電流擾動作一深入之探討。吾人發現,局部儲存方式明顯地增加RTN的擾動。而RTN的振幅隨著不同的寫入準位而改變。用一機率模型,可定義此RTN造成的讀取電流擾動分佈。例外,利用較好的底部氧化層製程方法,可有效降低此讀取電流雜訊。 最後於第八章,吾人將對本論文做個總結。
This thesis will focus on the reliability issues of SONOS-type trapping storage flash memories. For today’s SONOS cells, a thicker bottom oxide is employed to improve the retentivity. These cells exhibit excellent data retention behavior before stress. After P/E cycling, the bottom oxide is damaged, thereby degrading the reliability. In Chapter 1, the device structure and program/erase methods of the cell are described. A reverse read scheme for two-bit operation is illustrated. With respect to the cell endurance, the threshold voltage in program-state or in erase-state may shift upward as P/E cycle number increases. The mechanism will be investigated in Chapter 2. To expound the second-bit effect, a modified charge pumping technique to characterize programmed charge lateral distribution is proposed in Chapter 3. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the secondly programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases. Reliability issues including erase-Vt state threshold voltage instability, read-disturb, and high-Vt state charge loss will be addressed in Chapter 4. First, an erase-state threshold drift with storage time is observed in a P/E cycled cell. This drift has insignificant temperature dependence and exhibits an anomalous turn-around with P/E cycle number. This peculiar phenomenon is strongly related to the creation of positive charged defects in the bottom oxide. The temporal evolution of the threshold voltage drift has log(t) dependence on storage time and can be well described by the tunneling front model. Furthermore, at a sufficiently large read bias, positive charge assisted channel electron tunneling dominates the threshold voltage shift, causing a power-law time relation. By measuring the dependence of electric field and temperature, an analytical model based on Frenkel-Poole emission followed by oxide trap assisted tunneling successfully identifies the mechanism for charge loss. With use this model, a Vg acceleration method for retention lifetime test is also proposed. Bottom oxide thickness and program/erase stress effects on charge retention in SONOS flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron trapping model, the electron retention behavior in a SONOS cell with bottom oxide thickness from 1.8nm to 5.0nm is simulated. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole excitation of trapped electrons to the conduction band and electron re-capture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via positively charged oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide is included to describe various charge leakage paths. We measure the nitride charge leakage current directly in a large area device for comparison. Our study reveals that the charge retention loss in a high-voltage stressed cell with a thicker bottom oxide (5nm) exhibits two stages. The charge leakage current is limited by oxide trap assisted tunneling in the first stage and then follows a 1/t time dependence due to the Frenkel-Poole emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap assisted tunneling time, but is prolonged by a factor. According to the above understanding, the silicon nitride trap density can be extracted from the 1/t transient current in Chapter 6. In Chapter 7, program/erase stress induced read current fluctuation arising from random telegraph noise (RTN) in a localized, multi-level SONOS cells is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution caused by RTN is characterized and modeled. Better bottom oxide process can reduce read current noise. Conclusions are finally made in Chapter 8.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009011808
http://hdl.handle.net/11536/80581
Appears in Collections:Thesis


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