標題: Gbps高速渦輪碼之設計與實現
Design and Implementation of Gbps Turbo Decoders
作者: 賴名威
李鎮宜
電子研究所
關鍵字: 渦輪碼;高速;平行;turbo code;high speed;parallel
公開日期: 2006
摘要: 自九零年代初渦輪碼被發現以來,由於出色的錯誤更正能力一直以來廣泛的引起研究者的注意,在近期寬頻無線通訊以及第四代行動通訊等協定中,對於高速渦輪碼的資料流量的要求,也分別訂定了每秒70Mb以及每秒20Mb到100Mb的高速傳輸量,因此,對於高速渦輪碼的需求也與日俱增。而在渦輪碼的解碼中,由於尋找最大事後機率的解碼方式中,含有遞迴式的計算方式,也因此造成了在渦輪碼的解碼中,產生了很可觀的時間延遲。在這篇論文當中,針對高速的渦輪碼解碼,我們提出了一個完整的解決方案,其中,包含一個資料讀寫平順無誤的打散器設計,一個多級高階的渦輪解碼器,以及提出ㄧ種能夠運用在兩個維度的平行解碼器架構,由於這些因素,使得我們在本論文中所提出的設計,與現今科技之水準比較下,達到最高的能源效率以及每秒的資料解碼量,達到最高的水準。
Turbo codes have received a lot of interest since 90’s because of their excellent performance. To apply turbo codes in high-speed digital communications, such as in broadband wireless access based on the IEEE 802.16 standard supporting data rates of up to 70 Mb/s, and in fourth generation cellular systems, which are expected to provide a data rate from 20 to 100 Mb/s for high mobility, high throughput of turbo codes is a critical issue. The recursive computations in the MAP-based decoding of turbo codes usually introduce a significant amount of decoding delay. In this thesis, we present a total solution for a high throughput application, including a contention-free interleaver design, a high radix turbo decoder design, and the two-dimension parallel decoding architecture. The chip proposed in this thesis is the most power efficient and the fastest design in the state of the art.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411643
http://hdl.handle.net/11536/80554
Appears in Collections:Thesis


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