標題: 具有四相位電壓控制震盪器用在超寬頻帶頻率合成器的互補式金氧半導體鎖相迴路
CMOS Phase Lock Loop with Quadrature Voltage-Controlled Oscillator for Ultra Wide Band (UWB) Frequency Synthesizer
作者: 許晏維
Yen-Wei Hsu
吳重雨
Chung-Yu Wu
電子研究所
關鍵字: 超寬頻;頻率合成器;鎖相迴路;UWB;synthesizer;PLL
公開日期: 2008
摘要: 具有超寬操作頻率高傳輸速率由IEEE 802.15 TG3a制定的超寬頻通訊系統已被視為次世代通訊系統的主軸。在最近幾年,7128-MHz附近的頻帶中,已有7.5-GHz的頻寬由美國國家通訊委員會(FCC)釋出作為高速短距離通訊系統使用。此頻帶具有可應用在高達數百-百萬位元等級的高傳輸速率無線個人網路(WPAN)以及點對點傳輸的潛力. 此論文中介紹了一個應用在超寬頻帶的全頻帶頻率產生的系統結構和其中的一個有兩級環式震盪器的鎖相迴路電路實現。此全頻帶頻率產生的系統中包含了使用最少數目的SSB混波器、統一的輸出級以及兩個固定除數的鎖相迴路等電路並且使用了0.13-um CMOS技術來設計。藉由使用兩級的環式震盪器,所需要的操作頻率不需要額外的電路而可以容易的達到,且環式震盪器具有高度的整合性。進一步來說,在IC中它可以節省更多的功率消耗和晶片面積。本電路的輸出相位雜訊在1 MHz偏差下是-117.6 dBc/Hz 而功率頻譜是-0.313 dBm。在1.2-V的電源下,當震盪器輸出在所需的頻率7128 MHz時,其直流的功率消耗是12.42 mW。而頻率可以調整的範圍在控制電壓1.1 V~0.1 V時,是5.8 GHz~8.8 GHz。 除了震盪器電路,除頻器電路是在不同的操作頻率下選擇不同的的電路架構以節省功率的消耗。而相位頻率偵測器是使用一般的結構並且在操作頻率500 MHz以下都可以正確的工作。而充電幫浦的充放電流不匹配比率在控制電壓1.1 V~0.1 V時,都在4 %以下。最後的迴路濾波器是由國家半導體提供的程式來設計的二階濾波器,並由Matlab寫的程式來做二次驗證已求其相位極限(phase margin)大於60度。在預估輸出負載在100 fF下,整個鎖相迴路所消耗的功率大約是在29 mW,頻道內的突波抵抗程度是-53dBc。
In the next-generation wireless communication as UWB applications, high data rate transmission with a wide operating frequency spectrum is expected to be realized by 802.15.3a Task Group specification. Over the past few years, the 7.5-GHz frequency spectrum divided into 14 bands around 7128 MHz has been released by FCC for unlicensed use in high-speed and short-range communication systems. It has great potential in application of high data-rate wireless personal–area network (WPAN), high speed WLAN and point-to-point link, with possible data rate of hundreds of megabits per second. In this thesis, a full-band frequency spectrum generation scheme for UWB applications and a phase lock loop with two-stage ring oscillator are presented. The proposed full-band frequency spectrum generation scheme which consists of the least single-side-band mixers, a unified output port, and two division-number fixed PLL. The higher output frequency PLL is designed by using 0.13-um CMOS technology. Utilizing a two-stage ring oscillator, the operating frequency of the PLL can be achieved effortlessly without other circuit component. It also has high integration for ICs. Furthermore, it saves more power consumption and chip area in integrated circuits. The output phase noise of the oscillator is -117.6 dBc/Hz at 1 MHz offset and the power spectrum is -0.313 dBm. The power consumption of the two-stage ring oscillator is 12.42 mW from 1.2-V power supply at the required output frequency 7128 MHz. The tuning range of the oscillator is 5.8 ~8.8 GHz under 1.1~0.1 control voltage. Besides oscillator, the divides are chosen different architectures for different operation frequencies to economize on power consumption. Phase and frequency detector is using the conventional structure that cost small power consumption and could function correctly under operation frequency 500 MHz. The mismatching ratio of the proposed current-match charge pump is 4 % under the control voltage 0.1V~1.1V. Finally, the loop filter is designed by the loop filter design software from National Semiconductor as second order structure and double check with Matlab code to let the phase margin higher than 60 degrees. The overall power consumption of the proposed PLL is around 29 mW at estimation output loading 100 fF. The in band spur rejection is -53 dBc.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411639
http://hdl.handle.net/11536/80551
Appears in Collections:Thesis


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