標題: 應用於Serial ATA 6Gb/s 之展頻時脈產生器
A Spread Spectrum Clock Generator for Serial ATA 6Gb/s Application
作者: 黃彥穎
HUANG YEN YING
周世傑
Shyh-Jye Jou
電子研究所
關鍵字: 鎖相迴路;展頻電路;Phase Locked Loop;phase interpolation;phase rotation;spread spectrum clocking
公開日期: 2007
摘要: 展頻技術主要是對時脈信號的頻率做調變,使得信號能量平均分散到較為寬大的頻譜內。降低其在頻譜上相對應的能量峰值。本論文先簡單的介紹鎖相迴路的設計觀念,並提出了展頻的穩態以及暫態現象的分析與鎖相迴路系統參數的關係,使得我們可以得到一個較佳的設計概念。並解決了在多工器操作之下,所造成不當的信號突波。為了保證電路操作的穩定性,我們同時採取了數位控制的解決方法,來保證相位變化是單調且一致的。在鎖相迴路中,為了減小時脈抖動,我們採取錯誤放大器的方式來解決電路操作中電流不匹配的問題,同時採用三階迴路濾波器濾除鎖相迴路中週期性的突波現象。我們在振盪器中加入被動電阻,以降低對震盪器輸入端的敏感度並提高線性度;又加入交互偶合電晶體來加速震盪器震盪轉態的操作。 我們所提出的展頻時脈產生器主要應用於Serial ATA 6Gbps中,向下展頻5000ppm同時採用三角波調變且調變頻率為30KHz。此展頻時脈產生器使用和差調變器及相位旋轉方式完成之。此電路是在90奈米互補式金氧半的製程下所製造。展頻時脈最大週期對週期時脈抖動為1.13ps並操作在1.4GHz時消耗7.57毫瓦。能量峰值所能降低的最大數量為20.6dB。晶片面積分為: 鎖相迴路主要電路 ,迴路濾波器 ,相位旋轉單位 。
Spread spectrum is to modulate the frequency of clock and to spread the clock energy in a wider spectrum. This would lead to a reduction of the peak level of the clock energy. In this thesis, we will describe the phase-locked loop (PLL) design considerations first. Then, we will introduce the steady-state and transient analysis of spread spectrum behavior. These can help us to express the SSCG design consideration with PLL parameters. We also use the interpolation technique to avoid the glitch problem due to the operation of multiplexer and provide a thermal code control to guarantee the monotonic behavior in the process of phase rotation. In the PLL design, we achieve low jitter issue by using error amplifier to resolve the current mismatch in charge pump and a third order loop filter is adopted to reduce the reference spur. A passive resistor is presented in the VCO delay cell to reduce the Kvco gain and an additional cross-couple CMOS is also included to the delay cell to boost the operation of delay cell. Our spread spectrum clock generator (SSCG) for Serial ATA Specification is down spread 5000ppm with a triangular modulation profile and the modulation frequency is 30 kHz. A spread spectrum technique using PLL with a sigma delta modulator and phase rotation algorithm is proposed. This proposed architecture has been designed in a 90-nm CMOS process. The spread clocking has a peak-to-peak cycle-to-cycle jitter of 1.13ps and consumes 7.57mW at 1.4GHz. The EMI reduction in this circuit is about 20.6dB. The core area includes PLL Main Circuit ( ), Loop Filter ( ) and Phase Rotation Block ( ).
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411628
http://hdl.handle.net/11536/80540
Appears in Collections:Thesis


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