標題: 低成本高效率內容適應性可變長度編碼器之設計
A Low Cost and High Throughput CAVLC Encoder Design
作者: 吳秈璟
Sian-Jing Wu
張添烜
Tian-Sheuan Chang
電子研究所
關鍵字: 內容適應性;CAVLC
公開日期: 2006
摘要: 本論文提出一個低成本高效率的內容適應性可變長度編碼器。本論文的動機是為了補償編碼區塊樣式先決的低效能以達到高效率,使得我們所提出的內容適應性可變長度編碼器能支援每秒處理30張1080p畫面。此外,在如此高效率之下,我們必須維持少量的邏輯閘。編碼區塊樣式先決能跳過一些零方塊的編碼流程來提高效率。然而,我們的統計數據指出有大量的零係數無法被編碼區塊樣式先決偵測到,使得許多的週期數被浪費在零係數。在我們的設計裡,除了採用編碼區塊樣式先決,我們還使用可以直接對非零係數作編碼的新奇架構,以避免花費時間在零係數:零方塊碼字表與非零索引表。 當我們所提出的內容適應性可變長度編碼器在一個週期內讀取一個方塊的所有係數時,非零索引表同時記錄那些係數是非零的。然後非零索引表會分辦這個方塊是否為全零。假如這方塊是全零,零方塊碼字表可以在不用跑完整套內容適應性可變長度編碼流程的情況下,直接產生這個方塊的全部碼字。另一方面,如果這個方塊含有至少一個非零係數,非零索引表使用組合電路找出非零係數的位置,使得零係數被忽略。再者,當非零索引表鎖定一個非零係數時,這個非零係數的碼字會直接被連接到H.264/AVC的位元串流。因此,我們不需要額外的緩衝存儲器來儲存這個非零係數,使得少量的邏輯閘被消耗。 最後,基於聯華電子點一三微米製程,我們所提出的設計在145 MHz的工作時脈之下,消耗了9.03 K個邏輯閘,且可支援每秒處理30張1080p的畫面。和其它的設計相較之下,我們可以節省61%的邏輯閘與29%的週期數。
This thesis proposes a low cost and high throughput CAVLC encoder. The motivation is to compensate the inefficiency of CBP Look-Ahead to achieve higher throughput such that the proposed CAVLC encoder can support 1080p at 30 fps. Moreover, under such high throughput, we must keep logic gate count low. CBP Look-Ahead can skip encoding flow of some zero blocks such that throughput can be improved. However, our statistics show that abundant zero coefficients cannot be detected by CBP Look-Ahead such that many cycle counts are wasted on the zero coefficients. In our design, we use novel direct significance encoding architectures, as well as CBP Look-Ahead, to avoid spending time on zero coefficients: Zero-block Codeword Table and Nonzero Index Table. Nonzero Index Table concurrently records which coefficients are significant while the proposed CAVLC encoder is reading all coefficients of a block in one cycle. Then Nonzero Index Table determines whether the block is all-zero. If the block is all-zero, Zero-block Codeword Table will generate the overall codeword of the block without going through the whole CAVLC encoding flow. On the other hand, if the block consists of at least one significant coefficient, Nonzero Index Table uses combinational circuits to locate significant coefficients such that zero coefficients are ignored. In addition, while Nonzero Index Table is aiming for a significant coefficient, the codeword of the significant coefficient can be directly concatenated into the H.264/AVC bit-stream. Hence, we do not need additional buffers to store the significant coefficient such that small logic gate count is consumed. Eventually, based on 0.13um UMC technology, the proposed design can support 1080p at 30 fps while consuming 9.03 K gate count at 145 MHz. Compared with other designs, we can reduce 61% logic gate count and 29% cycle count.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411612
http://hdl.handle.net/11536/80524
Appears in Collections:Thesis


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