標題: 適用於展頻時脈之多重交替式轉態取樣技術與時脈資料回復電路
Clock and Data Recovery for Spread Spectrum Clock using Multiple Alternating Edge Sampling
作者: 鄭元樸
Yuan-Pu Cheng
周世傑
Shyh-Jye Jou
電子研究所
關鍵字: 時脈資料回復電路;展頻;交替式轉態取樣;相位內插器;鎖像迴路;Clock and Data Recovery;Spread Spectrum;Alternating Edge Sampling;Feed-Forward;Phase interpolator;Phase Locked Loops
公開日期: 2007
摘要: 在本論文中,我們提出一個操作在6Gbps,符合SATA第三代規格的時脈資料回復電路。本設計具備了頻率合成迴路與時脈回復迴路之雙迴路,其各自獨立的特性使得它適合應用在多通道的串列傳輸。而數位實現的時脈資料回復演算法可針對不同應用而彈性調整其迴路特性,可增加應用性與可靠度。二階的數位迴路演算法可以克服頻率上的誤差並可適用於展頻資料加以追蹤與回復,並符合SATA第三代的要求。在迴路中所使用之相位內插器高達1/32位元時間的相位解析度使得相位追蹤誤差小而不致增加位元錯誤率。 在高速時脈資料回復電路中,二元相位偵測器是主流的趨勢。但是二元相位偵測的非線性行為卻會為相位追蹤迴路帶來諸多不利影響,如:增益隨抖動量改變、穩態下震盪等。因此我們提出「多重交替式轉態取樣技術」,能有效的使二元相位偵測器的增益線性化,從而達到高速且穩定的相位追蹤。 實作晶片使用聯電標準臨界電壓90奈米互補式金氧半導體製程來製造,佈局後之模擬的資料頻率為5.5Gbps到6.5Gbps,回復時脈的峰對峰抖動值為17.52ps。在操作電壓源為1.0V之下,電路總體功率為55mW。
In this thesis, we propose a CDR circuit that operates at 6Gbps and conform to specifications of SATA generation three. This design incorporates dual-loop, the frequency synthesize loop and clock/data recovery loop are independent from each other, making this CDR suitable for multi-channel serial link applications. The digitally implemented phase tracking algorithm is programmable to change the loop characteristic for different jitter conditions, enhancing the applicability. The 2nd-order digital loop algorithm can track frequency deviation and is therefore suitable for spread spectrum clock transmission. The tracking for SSC conforms to SATA generation three specifications. In the loops, The phase interpolator has a resolution of 1/32 UI and is enough to keep phase error small and BER low. In the high speed CDR, binary phase detection is the mainstream. However the non-linear characteristic of binary phase detection introduces unwanted effects like PD gain varies with jitter amplitude, and oscillatory steady state of phase tracking. Therefore we propose the Multiple-Alternating Edge Sampling (M-AES) to linearize the PD gain and acquire high speed and stable phase detection. The test chip is fabricated in UMC 90nm CMOS regular-Vt process. The post-layout simulated data rate from 5.5Gbps to 6.5Gbps, the peak-to-peak jitter is 17.52ps. The analog circuit power consumption is 55mW under 1.0V supply voltage.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411594
http://hdl.handle.net/11536/80509
Appears in Collections:Thesis


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