標題: 利用矽鍺氧與矽鍺氮薄膜形成鍺奈米點在非揮發性記憶體應用之研究
Study on Formation of Ge Nanocrystal using SiGeO and SiGeN layer for Nonvolatile Memory Applications
作者: 謝彥廷
Yen-Ting Hsieh
張俊彥
Chun-Yen Chang
電子研究所
關鍵字: 記憶體;非揮發性;奈米點;鍺;Memory;Nonvolatile;Nanocrystal;Germanium
公開日期: 2006
摘要: 近年來,可攜帶式電子產品被廣泛的使用,諸如數位像機、筆記型電腦、手機等等的產品,在市場上佔有重要的地位。而這些產品都需要運用到非揮發性記憶體(NVM)作為儲存資料中心,而非揮發性記憶體目前在元件尺寸持續的微縮下,其需求為高密度記憶單元、低功率損耗、快速讀寫操作以及良好的可靠度(Reliability)。然而傳統浮動閘極(floating gate)記憶體在操作過程中,穿遂氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基版,隨著尺寸微縮這種情況會更糟,所以在資料保存時間(Retention)和耐操度(Endurance)的考量下,微縮穿遂氧化層的厚度是非常困難的。非揮發性奈米點記憶體及SONOS記憶體被提出希望可取代傳統浮動閘極記憶體,由於彼此分離的儲存點作為儲存中心,所以上述兩者可以有效改善小尺寸記憶體元件多次操作下的資料儲存能力。 在本文中,我們提出一種矽鍺氧(SiGeO)的堆疊結構作為作為鍺奈米點(Ge nanocrystal)的自我析出層(self-assembled layer),並應用在奈米點非揮發性記憶體上。在室溫下,在氬氣及氧氣(Ar/O2)的環境中濺鍍(sputtering)矽鍺(SixGe1-x)混合靶材,此方式可以成功的將氧摻入至矽鍺中形成矽鍺氧三元薄膜,另外,在我們的實驗中,在熱退火之前先疊加上一層氧化矽為一個關鍵的步驟。之後我們再利用矽與鍺不同的氧化現象,經由快速熱退火製成來形成均勻且高密度(~1012cm-2)的鍺奈米點。並且我們延長熱處理的時間可以有效的分離鍺奈米點且減少奈米點周圍氧化矽及氧化矽中的缺陷(defects),有效的降低電荷流失機率,改善資料保存時間。 同樣地,我們用相同的方式,在濺鍍的過程中將氧氣置換成氮氣,利用同樣的方式製作鍺奈米點且被包覆在氮化矽(SiNx)的結構,其記憶效應比先前的鍺奈米點埋在氧化矽(SiOx)結構還顯著,此乃因為鍺奈米點埋在氮化矽為主的載子儲存層中,會產生額外的儲存中心,進而增加記憶體效能,另外,我們也延長熱處理的時間,同樣低可以改善鍺奈米點間的隔離情況得到較大的記憶窗口,且改善資料保存時間。 另外,我們也嚐試利用高介電常數介電質(ErSiGeO)當作我們的電荷儲存層,可以有效的增加記憶體效應,且改善寫入讀取速度。以上這些應用在非揮發性記憶體的製成技術同時也適用於現階段積體電路製程。
In recent years, the portable electronic products have widely applied, such as digit camera, laptop, cell phone and so on. These portable electronic products play an important role in the market, and these products are all based on the nonvolatile memory (NVM) for data storage center. Hence, the current requirements of NVM are the high density cells, low-power consumption, high-speed operation and good reliability for scaling down devices. However, all of the charges stored in the conventional floating gate NVM will leak back to substrate because the tunnel oxides have leakage paths during operation processes. It is even worse when being scaled down. Therefore, the thickness of tunnel oxide is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memory and SONOS memory are promising candidates to replace the conventional floating gate memory, because the discrete storage nodes of themselves are enveloped. Both of them are capable to improve data retention under operation and have been provided by the endurance test which is good for device further down scaling efficiently. In this thesis, we proposed a SiGeO stacking structure serving as Ge nanocrystals self-assembled layer for application of nanocrystal NVM. We successfully incorporated oxygen into SiGe layer to form SiGeO ternary film by sputtering commixed SixGe1-x target in an Ar/O2 ambiance at room temperature. In additional we fond out that pre-annealing-capping oxide (PACO) is a critical step in our experimental process, and then we used the different oxidized mechanism between Si and Ge. The uniform and high density (~1012cm-2) of Ge nanocrystals was fabricated after a rapid thermal annealing (RTA) process. The Ge nanocrystals were isolated better and the defects (leakage path) in the SiOx which surrounds the nanocrystal were reduced by increasing the thermal treatment time. This process can reduce the probability of charges losing and improve the data retention time. As the same, we used similar method that oxygen was replaced by nitrogen. The Ge nanocrystals embedded in SiNx structure was fabricated by using the same process. The memory window for the stacked structure with Ge NCs embedded in SiNx layer is larger than Ge NCs embedded in SiOx layer, due to the extra charge trapping centers generated for Ge NCs embedded SiNx layer. Furthermore, we also increased the time for thermal treatment resulting in better Ge NCs isolation and less defects in the SiNx. That improves the data retention time, too. In addition, by using high dielectric constant layer (ErSiGeO) for charging tapping layer structure has better memory ability and the operation speed is improved, too. Finally, all of the above fabrication techniques for the application of nonvolatile nanocrystal memory can be compatible with current manufacture process of the integrated circuit manufacture.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411553
http://hdl.handle.net/11536/80466
Appears in Collections:Thesis


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