標題: 具有奈米線通道的薄膜電晶體之氮化矽記憶體元件特性分析
Characterization of TFT-SONOS with Nanowire Structure
作者: 黃建富
Jian-Fu Huang
黃調元
林鴻志
Tiao-Yuan Huang
Horng-Chih Lin
電子研究所
關鍵字: 氮化矽記憶體;奈米線;薄膜電晶體;雙閘極;SONOS;nanowire;TFT;double gate
公開日期: 2006
摘要: 在本篇論文中,我們使用邊襯(sidewall spacer)過度蝕刻的方法製作具有奈米線通道之薄膜電晶體的氮化矽記憶體,另外還進一步結合了雙閘極的概念,並且對基本電特性、寫入/抹除速度、可靠度做詳細的分析討論。 我們利用奈米線結構來提高對通道的控制能力,而且有效的降低臨界電壓(threshold voltage)、漏電流以及次臨界擺幅(subthreshold swing),其基本電特性較一般標準結構的薄膜電晶體為好。 因為元件通道由多晶矽組成,通道中有很多由晶粒邊界(grain boundary)造成的能障,阻礙電子從源極加速到汲極,所以我們捨棄通道熱電子注入(CHEI),改用FN穿隧來寫入/抹除資料。由於奈米線高敏感的特性,使元件擁有不錯的寫入/抹除速度。在可靠度方面,我們發現利用雙閘極的結構可以改變電子儲存的位置,因此調整上閘極的偏壓使電子儲存在距離穿隧氧化層較遠的位置,進而增加資料的保存能力。不過在重複寫入/抹除耐久性的表現上,並沒有因為雙閘極的結構而改善。耐久性差的主要原因,是因為使用TEOS當作穿隧氧化層,而TEOS的品質較乾氧化層差,容易產生缺陷;再加上因為通道尖角造成的局部大電場會對穿隧氧化層造成極大的傷害,所以特性並不理想。不過,我們相信只要能製作出品質較好的穿隧氧化層,並且平緩通道的尖角,耐久性是可以獲得改善的。
In this thesis, TFT-SONOS with nanowire structure was fabricated by sidewall spacer over-etching technique. In addition, the double-gated configuration was also studied. The electrical characteristics, programming and erasing characteristics, and reliability of NW-SONOS were studied and discussed in detail. The nanowire structure was employed in this thesis to enhance the channel control by taking advantage of its high surface-to-volume ratio. We confirmed that it indeed improves the threshold voltage, leakage current, and subthreshold swing of the resultant devices. In short, the electrical characteristics of NW-TFT are better than those of the conventional TFT. Since the channel in our device is composed of poly-Si material, there exist many barriers arising from the grain boundaries in the channel. These barriers tend to block the electrons in the source from accelerating toward the drain. To avoid this disadvantage, the CHEI mechanism is replaced with FN tunneling for programming and erasing operations in our device. Due to the high sensitivity of nanowire structure, the proposed NW-SONOS indeed depicts good programming and erasing characteristics. In order to improve the reliability characteristics, the double-gated structure was employed to shift the location of the trapping charges. Specifically, the electrons can be trapped further away from the tunneling oxide by adjusting the top-gate bias, improving the data retention characteristics. It should be noted, however, that the double-gated structure does not seem to improve the endurance characteristics of the device. The poor endurance is ascribed to the poor quality of TEOS used for the tunneling oxide as well as the horn-shaped channel. The traps are easily generated because of poor quality of TEOS. Besides, high electric field due to the horn of the channel could seriously damage the tunneling oxide. We believe, however, that the endurance could be improved by optimizing the quality of the tunneling oxide, and/or smoothing the shape of the channel in the future.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411546
http://hdl.handle.net/11536/80460
Appears in Collections:Thesis


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