The Study of Crystallization Schemes and Novel Structures in Low Temperature Poly-Si Thin-Film Transistors
在本論文中，首先，我們研究利用氬氣(Argon)的離子佈植去改善複晶矽薄膜電晶體的特性，透過這種新穎的表面成核機制，不但會使複晶矽的結晶顆粒變大而且結晶的缺陷也會被抑制住而變少，因此，我們能得到高品質的複晶矽通道，我成功地將氬氣離子佈植的薄膜電晶體做出來而且我的實驗結果顯示和傳統薄膜電晶體相較之下它有很好的場效載子移動率(46.06 cm2/Vs)和低密度的晶粒邊界補陷能階(grain boundary trap state)(3.44 × 1012 cm-2)。
最後，我們研究利用間隙壁(spacer)技術來做複晶矽薄膜電晶體的奈米線通道，此種元件結構的特色就是在你定義的線條側壁上留下自動對準的複晶矽奈米線通道，這種成對式奈米線通道元件有很好的閘極控制能力因為它的結構類似三閘極式結構，而且也因為它的通道是奈米線使得複晶矽的晶粒邊界缺陷被抑制住，因此，這種元件有很好的電特性如有較高的ON/OFF電流比(>107)，不錯的次臨界擺幅(subthreshold swing)(395 mV/decade)。|
ABSTRACT In this thesis, first, we studied Enhanced performance of poly-silicon thin-film transistors (poly-Si TFTs) with Argon ion implantation. By adopting this novel surface-nucleation solid-phase-crystallization scheme, not only the grain size of poly-Si can be increased but also the intragranular defects can be suppressed effectively. Therefore, a high quality poly-Si film within the channel with better crystallinity is formed. Argon-implanted TFTs have been successfully fabricated and the experimental results demonstrate a superior field-effect mobility of 46.06 (cm2/Vs), a fewer grain boundary trap state densities of 3.44 x1012 (cm-2) than those of conventional TFTs. Then, Floating channel polycrystalline silicon thin-film transistors are studied and demonstrated having superior electrical characteristics in the Chapter 3. In comparing with the conventional TFTs, the fabricated floating channel TFTs has an electrical property about 200% improved. The achievement is highly attributed to the fact that, by adopting this novel crystallization scheme, both the grain size and the intragranular defects of polycrystalline silicon are effectively improved. Therefore, we have demonstrated here a promising structure which forms a high quality channel film and is especially suitable for the future high-performance large-area device applications. Finally, the electrical characteristics of thin-film transistors (TFTs) with poly-Si nanowire (NW) channels fabricated by a novel sidewall spacer technique are studied. The new device features a conventional planar structure with self-aligned poly-Si NW channels along the sidewall of the prepatterned dummy stripe. The proposed TFT with twin nanowire channels owns outstanding gate controllability owing to its three-dimensional tri-gate-like structure, and holds suppressed poly-Si grain bounday defects owing to its nanoscale dimension. Therefore, the fabricated NW TFT exhibits excellent electrical characteristics, such as a high ON/OFF current ratio (>107), a reasonable subthreshold swing (S.S.) of 395 mV/decade. These results suggest that the fabrication procedure of NW TFT is a very promising candidate for future practical manufacturing.
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