標題: 佈局參數對高壓金氧半場效電晶體電性影響之研究
A study on the influence of layout parameters on electrical characteristics of high-voltage MOSFETs
作者: 柳旭茹
Hsu-Ju Liu
崔秉鉞
Bing-Yue Tsui
電子研究所
關鍵字: 佈局參數;高壓;金氧半場效電晶體;電性;layout;parameters;high-voltage;electrical;characteristics;MOSFET
公開日期: 2007
摘要: 隨著半導體製程的發展,自七零年代至今,高壓高功率元件已由以閘流體與雙極功率電晶體為主的市場,逐漸發展到現今的高功率金氧半場效電晶體,由於高壓功率金氧半場效電晶體之低成本、切換速度快與其功率消耗較低的優勢,因此,已成為現今工業界中,最易與低電壓之傳統互補式金氧半場效電晶體的製程技術整合在一起者,多被設計用於控制與承載較高電流且耐高壓的高功率積體電路。 在本論文主要探討佈局參數對高壓金氧半場效電晶體電性上的影響趨勢,包括︰電晶體內閘極汲極間淺溝式隔離之長度(S參數)、汲極基極間淺溝式隔離之長度(d參數)、閘極電極覆蓋在淺溝式隔離上方之長度(a參數)、與閘極電極下高壓N型植入井至淺溝式隔離邊緣之長度(b參數)等等,先藉由實驗量測的結果,去探討在電性上,各個佈局參數對電晶體之影響,再以製程元件模擬軟體去模擬其結果與了解其發生的物理機制。 研究發現,高壓金氧半場效電晶體之臨界電壓與佈局參數皆無相關性。若欲提升高壓金氧半場效電晶體之崩潰電壓,可選擇將S參數拉長或將電晶體設計為對稱型的結構,但我們發現,將電晶體製作為對稱型的結構,其對耐壓的提升效果並不如直接將S參數拉長的效果來得顯著。至於d參數也不能設計得過短,因d縮小時將引發電晶體崩潰點的移轉,由原本閘極下通道處的累增崩潰轉移到外圍基極下的穿透崩潰。此外,亦發現b值會影響到電晶體之基體電流與熱載子效應,在實驗元件中當b值縮小至0.6μm時,將會引發相當高且持續增加的基極電流;並且,當b值設計在0.6μm時,因閘汲極間電流路徑的陡峭與電流的集中效應,故會使得導通電流大幅降低;欲改善此效應可試著將b值略微加長,但要注意b值亦不可過長,否則也會因電流路徑的拉長而造成導通電流的下降,故b值必須要視不同的電晶體構造來取得一個對元件特性的最佳值,值得進一步的研究。
With the progress of integrated circuit technology, high-voltage devices with high power have developed into the market of HV-MOSFETs from the market of thyristors and bipolar power transistors in 1970’s, which have become the most preferable devices to be integrated with the technology of conventional CMOS due to its low cost, fast switching speed, and low power loss. Hence, HV-MOSFETs are mostly-applied to not only control but also carry the high power ICs with high current nowadays. In this thesis, we study on the influence of layout parameters on electrical characteristics of high-voltage MOSFETs and those layout parameters include the length of shallow-trench-isolation between gate and drain (parameter S), the length of shallow-trench-isolation between drain and bulk (parameter d), the overlap between gate and shallow-trench-isolation (parameter a), and the length from HV-N well to the edge of shallow-trench-isolation under gate electrode (parameter b). In the beginning, we survey the electrical characteristics of different devices with various layout parameters, finding out the effect of each layout parameter according to the measured data and then use the simulation tool (ISE-TCAD) to figure out the physics inside the transistors and to explain how those layout parameters affect the electrical characteristics of HV MOSFETs. In this study, we find that layout parameters have nothing to do with the threshold voltage of HV-MOSFETs. To raise the breakdown voltage of HV-MOSFETs, it is useful to increase the length of parameter S or to design the transistor to be symmetric. However, we discover that the improvement from designing the transistor with symmetry is much less than that from the increase of parameter S. As for parameter d, it should be designed long enough to avoid the punch-through breakdown which occurs under the bulk electrode ahead of the conventional avalanche breakdown. Besides, we observe that parameter b can affect the substrate current and induce severe hot carrier effect when b shrinks down. At the same time, it is found that the on-current will drop as b decreases to 0.6μm because of the high resistance current path resulted from the current-crowding effect around the shallow-trench-isolation between gate and drain. The solution to these problems can be the increase on the parameter b. Nevertheless, quite a long parameter b may lower the on-current as well due to the longer current path it could build. Thus, according to different device structures, parameter b should be designed accurately to accomplish the optimal electrical characteristics, which is worth studying furthermore.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411533
http://hdl.handle.net/11536/80444
Appears in Collections:Thesis


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