標題: 利用低溫多晶矽技術於製造具有多晶矽奈米線通道的薄膜電晶體之研究
A Study of Thin-Film Transistors with Poly-Si Nanowire Channels Fabricated by LTPS Technology
作者: 黃育峯
Yu-Fong Huang
林鴻志
黃調元
Horng-Chih Lin
Tiao-Yuan Huang
電子研究所
關鍵字: 薄膜電晶體;奈米線;低溫多晶矽;固相結晶;金屬誘發側向結晶;閘極引致汲極漏電流;TFT;nanowire;LTPS;SPC;MILC;GIDL
公開日期: 2006
摘要: 在本論文中,我們採用兩種低溫多晶矽(LTPS)技術,來製造具有多晶矽奈米線 通道的薄膜電晶體。其中一種技術為固相結晶法(SPC),由於此新穎的奈米線薄膜電晶體具有其特有的佈局,會使得閘極引致汲極漏電流(GIDL)成為主要的漏電機制;我們藉由引入一額外的深層離子佈植,可以有效地抑制GIDL的發生;另外,亦藉由活化能萃取和電場強度模擬來進一步討論其機制。另一種技術為金屬誘發側向結晶法(MILC),和SPC的元件相比較,由於其通道內部結晶情形的改善,可以大幅增進元件特性;此外,在本研究中亦探討成核開口配置和退火溫度對元件特性的影響。
In this thesis, two low-temperature poly silicon (LTPS) technologies are adopted to fabricate TFTs with poly-Si nanowire (NW) channels. One is solid phase crystallization (SPC), where gate-induced drain leakage (GIDL) is found to be the most dominant leakage mechanism due to the unique layout feature in the proposed NW-TFTs. By introducing an additional deep ion implantation (I/I), the undesirable GIDL mechanism can be suppressed effectively. Both activation energy extraction and electric field strength simulation are also investigated for further discussion. The other is metal-induced lateral crystallization (MILC). Compared with SPC device, the performance of the MILC device is dramatically enhanced owing to the improvement of the film crystallinity. Besides, the impacts of seeding window arrangement and annealing temperature are also explored in this study.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411523
http://hdl.handle.net/11536/80436
Appears in Collections:Thesis


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