標題: 一個1.25GHz具有高解析度與8個相位輸出之數位控制震盪器,應用於全數位鎖相迴路
A 1.25GHz digitally controlled oscillator with high-resolution and 8-phase output for ADPLL
作者: 楊永祥
Yung-Hsiang Yang
蘇朝琴
ChauChin Su
電機學院IC設計產業專班
關鍵字: 高時間解析度;數位控制振盪器;全數位鎖相迴路;high timing resolution;digitally controlled oscillator;ADPLL
公開日期: 2007
摘要: 現代的系統單晶片(SoC)需要晶片內在的時脈產生器以及產生許多不同的頻率,來提供給其他子系統使用,一般常用鎖相迴路為基礎的時脈產生器來達成此任務;然而,鎖相迴路參數為了減少抖動量以及保持迴路的穩定度,因而必須依照輸出頻率以及頻率產生倍數來調整,現有之類比電路方式需要較長的設計週期。 本論文中,為了大幅降低高速傳輸之接收器硬體銷耗及設計的難度,提出了一個可操作在高振盪頻率(Giga Hz)、高解析度、多重相位(8個相位)輸出之數位控制振盪器電路(DCO),此DCO將應用於”8-phase output之1.25GHz的ADPLL”, 而此ADPLL再將應用於具有”2.5Gb/s之data-transceiver”。為了減少鎖相迴路之抖動量,所以,提出在數位控制振盪器中利用傳輸閘的寄生電容差值, 作為數位控制之延遲單元,藉此提高數位控制振盪器電路之時間解析度。在微調上時間解析度能夠依照使用驅動細胞單元的能力及數位控制之延遲單元的電容差異,作不同的選擇,相對於使用OAI-AOI細胞單元或三態緩衝器矩陣,具有較線性的時間解析度。 所提出的電路架構將被實現在TSMC 0.18um 1P6M CMOS製程,晶片面積為310um*220um(不包含PAD),其操作頻率範圍為1.06GHz到1.50GHz,平均的時間解析度為0.38ps,當振盪頻率為1.25GHz,其功率消耗為34.1mW。
Modern system-on-a-chip(SoC) processors often require on-chip clock generation and multiplication to produce several unrelated frequencies for other sub-systems. The PLL-based clock generator is a common way of frequency multiplication to accomplish the task. However, the loop parameters must be adjusted to minimize jitter performance and insure stability for each output frequency and multiplication factors. Conventional analog skills suffer from long design cycle. In order to reduce the hardware overhead and the design complexity of high speed transceiver, the proposed digitally controlled oscillator has high operation frequency (GHz), high timing resolution, and multi-phase output (8-phase). The proposed DCO can be applied to “a 1.25GHz ADPLL with 8-phase output” and “a 2.5Gb/s data-transceiver architecture”. In order to reduce jitter of PLL, therefore, we propose the digitally controlled oscillator (DCO) with novel digital controlled delay cell based on parasitic capacitance difference of transmission gates. This method can enhance the timing resolution of the digitally controlled oscillator (DCO). The timing resolution in fine-tuned stage can be decided from different driving cells and capacitance difference of each digital controlled delay cell. Thus, a high resolution DCO with better timing linearity as compared with OAI-AOI cell or tri-state inverter matrix is achieved. The proposed digitally controlled oscillator circuit is designed using TSMC 0.18um 1P6M CMOS process with active die area of 310um*220um. The operation frequency range is 1.06GHz to 1.50GHz. Average timing resolution is 0.38ps. The total power consumption of the proposed DCO is 34.1mW when oscillate frequency is 1.25GHz.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009395525
http://hdl.handle.net/11536/80360
Appears in Collections:Thesis


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