Title: 9-25GHz寬頻CMOS LNA設計
9-25GHz Wideband CMOS LNA Design
Authors: 洪祺源
Qi-Yuan Horng
胡樹一
Shu-I Hu
電機學院電子與光電學程
Keywords: 寬頻放大器;寬頻LNA;Wideband LNA;Wideband low noise amp
Issue Date: 2008
Abstract: 本論文研製之主要目的是想要利用0.18um RF-CMOS 製程,來達成 9− 25GHz 寬頻LNA 的應用,因為目前0.18um CMOS 製程的寬頻LNA,大都為3− 10GHz 的設計,相對於目前所發表的論文,0.18um 製程的窄頻LNA 操作頻率已能達到24GHz。所以本專題目的就是使用便宜的0.18um CMOS 製程去設計一個能操作在Ka 頻段的寬頻LNA。 此電路設計是期望能利用L 和R-C 匹配方式,來達到寛頻及相對低的雜訊指數,並把它實現應用在nMOS 0.18um 的製程上,在CIC 量測的結果顯示,S21 可以達到10-16dB 的增益,在9GHz 的雜訊指數約為4.5dB。當操作的Vdd範圍在1.2− 2.0 伏特時,功率消耗為58−111mW。此晶片的大小為0.945 x 1.295 mm²。
A procedure is to introduce a 9−25GHz wide band LAN design which uses 0.18um RF-CMOS technology. In general, the 0.18um CMOS LNA usually be designed for 3−10GHz operating range. Otherwise, the narrowband LNA design already is proved that it can work at 24GHz. So, we would like to design a LNA and it can work at Ka band. The CIC measured result shows LNA S21 has 10-16dB gain and it has 4.5dB noise figure when operate at 9GHz, with 58−111mW power consumption for Vdd ranging from 1.2−2.0V. The chip size is 0.945 x 1.295mm².
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009367519
http://hdl.handle.net/11536/80076
Appears in Collections:Thesis


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