標題: 可動態重組之處理單元於頂點與像素處理
A dynamically reconfigurable shader unit for vertex and pixel processing
作者: 陳逸麒
Yi-Chi chen
鍾崇斌
Chung-Ping Chung
資訊科學與工程研究所
關鍵字: 可重組化架構;頂點處理器;像素處理器;可動態重組;Reconfigurable architecture;vertex shader;pixel shader;dynamically reconfigurable
公開日期: 2005
摘要: 在頂點與像素的處理中,頂點與像素的工作量,在執行過程中有大量的變化。然而在固定的硬體資源分配下,頂點處理器以及像數處理器經常有一方閒置,而另一方則發生資源不足的情況。為此,我們提出了一個新的shader unit: DR-shader unit,可針對工作量的變化,動態分配處理器於頂點或像素處理之數量,以提升硬體資源之使用率,並縮短執行時間。 在本論文中,首先分析處理器的架構,決定可動態重組處理器中,各元件是否能讓兩種組態所共用。其中我們利用最小繞線代價、最多共用邏輯以及最佳面積與時間三種演算法,幫助我們決定運算邏輯是否應作共用設計,以組合成運算單元。並且設計工作量監測邏輯,根據工作量的變化控制各可動態重組處理器之組態。最後得到於速度上有60%之提昇,以及30%使用率提昇。
In vertex and pixel processing, the workloads of vertices and pixels vary greatly during run time. However, in fixed resource allocation between vertex shaders and pixel shaders, many vertex or pixel shaders may be idle while the other type of shaders are insufficient. Therefore, we propose a dynamically reconfigurable shader unit (DR-shader unit) which can distribute shaders for vertex and pixel processing according various workloads during run time. By the way, shader utilization can be upgraded, shortening execution time In this thesis, we firstly analyze the architecture of shaders and determine shared units between vertex and pixel shader type in DR-shader. We use three algorithms: minimum routing overhead, maximum sharing logic, and optimal area-time to determine how logics be shared and complete sharable computation unit. Besides, we design workload monitor logic to control the configuration of each DR-shader by workloads. Finally we gain 60% upgrade in speed and 30% upgrade in utilization
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009323622
http://hdl.handle.net/11536/79152
Appears in Collections:Thesis


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  1. 362201.pdf