標題: 在晶片多處理器系統下以減少快取衝突為目的之動態工作排程方法
A Dynamic Task Scheduling Method for Less Cache Contention on Chip Multiprocessor Systems
作者: 廖哲瑩
Cheyin Liao
陳正
Cheng Chen
資訊科學與工程研究所
關鍵字: 晶片多處理器;工作排程;快取衝突;chip multiprocessor;task scheduling;cache contention
公開日期: 2005
摘要: 積體電路製程的進步使得需要大量電晶體來實作的微處理器設計得以被付諸實行,晶片多處理器 (chip multiprocessor) 是這些新世代設計的其中一員。一個晶片多處理器有多個處理器核心,在晶片多處理器上的L2快取記憶體會由這些處理器核心共用,因此處理器核心間可能會發生快取衝突。快取衝突會為晶片多處理器的效能帶來負面影響,為了減少快取衝突我們提出了一個稱為 Hint-aided Cache Contention Avoidance (HCCA) 的動態工作排程方法。 HCCA首先預測工作執行時可能使用的快取記憶體區段,並將會使用到相同快取記憶體區段的工作分開排程以減低快取衝突。在HCCA中包含三個階段,第一階段我們會由工作的程式碼中萃取出可以協助排班的資訊。接著,在第二階段我們會利用在第一階段萃取得來的資訊做出快取記憶體使用區段的預測。我們的預測是基於工作的程式碼所萃取得來的資訊,而工作的程式碼將會直接影響工作存取快取記憶體的模式,因此我們預期所做出的預測可以比其他的方法有較好準確率。最後,在第三階段我們根據於前一階段所做出的快取記憶體使用區段的預測結果做出工作排班。我們以模擬的方式評估HCCA的效能,模擬結果顯示HCCA可以使得晶片多處理器系統有較低的快取誤失率,並藉此可以改善整體效能。
The chip multiprocessor is an emerging microprocessor architecture which attempts to utilize the integration increased by the advances of integrated circuit technologies. A chip multiprocessor contains multiple execution cores which share the on-chip L2 cache. Therefore, the cache contentions may occur among cores. In order to reduce cache contentions which cause negative impacts on performance, we propose a task scheduling technique named Hint-aided Cache Contention Avoidance (HCCA). HCCA attempts to avoid cache contentions by separately scheduling tasks predicted to use the same cache sets. HCCA contains three phases. The first phase analyzes binary images and extracts information used to support the predictions of cache set usages. Then, the second phase makes the cache set usage predictions according to the information extracts by the previous phase. The predictions are made according to the information extracted from binary images which directly affect how tasks accessing cache sets. Therefore, the predictions are expected to be more accurate than those made by previous methods. Finally, the scheduling decisions are made in the third phase according to the cache set usages predictions made in previous phase. We have constructed a simulator to evaluate the performance of HCCA. The simulation results show that HCCA has lower L2 cache miss rate than that of others and also have some improvement on overall IPC compared with other methods.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009317562
http://hdl.handle.net/11536/78773
Appears in Collections:Thesis


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